MPC8260ADS.h 8.4 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Stuart Hughes <stuarth@lineo.com>
  4. * This file is based on similar values for other boards found in other
  5. * U-Boot config files, and some that I found in the mpc8260ads manual.
  6. *
  7. * Note: my board is a PILOT rev.
  8. * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /*
  29. * Config header file for a MPC8260ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
  30. */
  31. #ifndef __CONFIG_H
  32. #define __CONFIG_H
  33. /*
  34. * High Level Configuration Options
  35. * (easy to change)
  36. */
  37. #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
  38. #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */
  39. #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
  40. /* allow serial and ethaddr to be overwritten */
  41. #define CONFIG_ENV_OVERWRITE
  42. /*
  43. * select serial console configuration
  44. *
  45. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  46. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  47. * for SCC).
  48. *
  49. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  50. * defined elsewhere (for example, on the cogent platform, there are serial
  51. * ports on the motherboard which are used for the serial console - see
  52. * cogent/cma101/serial.[ch]).
  53. */
  54. #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
  55. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  56. #undef CONFIG_CONS_NONE /* define if console on something else */
  57. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  58. /*
  59. * select ethernet configuration
  60. *
  61. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  62. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  63. * for FCC)
  64. *
  65. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  66. * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  67. * from CONFIG_COMMANDS to remove support for networking.
  68. */
  69. #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  70. #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  71. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  72. #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  73. #if (CONFIG_ETHER_INDEX == 2)
  74. /*
  75. * - Rx-CLK is CLK13
  76. * - Tx-CLK is CLK14
  77. * - Select bus for bd/buffers (see 28-13)
  78. * - Half duplex
  79. */
  80. # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  81. # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  82. # define CFG_CPMFCR_RAMTYPE 0
  83. # define CFG_FCC_PSMR 0
  84. #endif /* CONFIG_ETHER_INDEX */
  85. /* other options */
  86. #define CONFIG_HARD_I2C 1 /* To enable I2C support */
  87. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  88. #define CFG_I2C_SLAVE 0x7F
  89. #define CONFIG_8260_CLKIN 66666666 /* in Hz */
  90. #define CONFIG_BAUDRATE 115200
  91. #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
  92. CFG_CMD_BEDBUG | \
  93. CFG_CMD_BSP | \
  94. CFG_CMD_DATE | \
  95. CFG_CMD_DOC | \
  96. CFG_CMD_DTT | \
  97. CFG_CMD_EEPROM | \
  98. CFG_CMD_ELF | \
  99. CFG_CMD_FDC | \
  100. CFG_CMD_HWFLOW | \
  101. CFG_CMD_IDE | \
  102. CFG_CMD_JFFS2 | \
  103. CFG_CMD_KGDB | \
  104. CFG_CMD_MII | \
  105. CFG_CMD_PCI | \
  106. CFG_CMD_PCMCIA | \
  107. CFG_CMD_SCSI | \
  108. CFG_CMD_VFD | \
  109. CFG_CMD_USB ) )
  110. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  111. #include <cmd_confdefs.h>
  112. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  113. #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
  114. #define CONFIG_BOOTARGS "root=/dev/ram rw"
  115. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  116. #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
  117. #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
  118. #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
  119. #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
  120. #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
  121. #endif
  122. #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
  123. /*
  124. * Miscellaneous configurable options
  125. */
  126. #define CFG_LONGHELP /* undef to save memory */
  127. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  128. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  129. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  130. #else
  131. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  132. #endif
  133. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  134. #define CFG_MAXARGS 16 /* max number of command args */
  135. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  136. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  137. #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  138. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  139. /* for versions < 2.4.5-pre5 */
  140. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  141. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  142. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  143. #define CFG_FLASH_BASE 0xff800000
  144. #define FLASH_BASE 0xff800000
  145. #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
  146. #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
  147. #define CFG_FLASH_SIZE 8
  148. #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
  149. #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
  150. /* this is stuff came out of the Motorola docs */
  151. #define CFG_DEFAULT_IMMR 0x0F010000
  152. #define CFG_IMMR 0x04700000
  153. #define CFG_BCSR 0x04500000
  154. #define CFG_SDRAM_BASE 0x00000000
  155. #define CFG_LSDRAM_BASE 0x04000000
  156. #define RS232EN_1 0x02000002
  157. #define RS232EN_2 0x01000001
  158. #define FETHIEN 0x08000008
  159. #define FETH_RST 0x04000004
  160. #define CFG_INIT_RAM_ADDR CFG_IMMR
  161. #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
  162. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  163. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  164. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  165. /* 0x0EA28205 */
  166. #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
  167. ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
  168. ( HRCW_BMS | HRCW_APPC10 ) |\
  169. ( HRCW_MODCK_H0101 ) \
  170. )
  171. /* no slaves */
  172. #define CFG_HRCW_SLAVE1 0
  173. #define CFG_HRCW_SLAVE2 0
  174. #define CFG_HRCW_SLAVE3 0
  175. #define CFG_HRCW_SLAVE4 0
  176. #define CFG_HRCW_SLAVE5 0
  177. #define CFG_HRCW_SLAVE6 0
  178. #define CFG_HRCW_SLAVE7 0
  179. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  180. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  181. #define CFG_MONITOR_BASE TEXT_BASE
  182. #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  183. # define CFG_RAMBOOT
  184. #endif
  185. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  186. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  187. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  188. #ifndef CFG_RAMBOOT
  189. # define CFG_ENV_IS_IN_FLASH 1
  190. # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
  191. # define CFG_ENV_SECT_SIZE 0x40000
  192. #else
  193. # define CFG_ENV_IS_IN_NVRAM 1
  194. # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  195. # define CFG_ENV_SIZE 0x200
  196. #endif /* CFG_RAMBOOT */
  197. #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  198. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  199. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  200. #endif
  201. #define CFG_HID0_INIT 0
  202. #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
  203. #define CFG_HID2 0
  204. #define CFG_SYPCR 0xFFFFFFC3
  205. #define CFG_BCR 0x100C0000
  206. #define CFG_SIUMCR 0x0A200000
  207. #define CFG_SCCR 0x00000000
  208. #define CFG_BR0_PRELIM 0xFF801801
  209. #define CFG_OR0_PRELIM 0xFF800836
  210. #define CFG_BR1_PRELIM 0x04501801
  211. #define CFG_OR1_PRELIM 0xFFFF8010
  212. #define CFG_RMR 0
  213. #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  214. #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  215. #define CFG_RCCR 0
  216. #define CFG_PSDMR 0x016EB452
  217. #define CFG_MPTPR 0x00001900
  218. #define CFG_PSRT 0x00000021
  219. #define CFG_RESET_ADDRESS 0x04400000
  220. #endif /* __CONFIG_H */