MBX.h 11 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * Configuation settings for the MBX8xx board.
  7. *
  8. * -----------------------------------------------------------------
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. /*
  28. * Changed 2002-10-01
  29. * Added PCMCIA defines mostly taken from other U-Boot boards that
  30. * have PCMCIA already working. If you find any bugs, incorrect assumptions
  31. * feel free to fix them yourself and submit a patch.
  32. * Rod Boyce <rod_boyce@stratexnet.com.
  33. */
  34. /*
  35. * board/config.h - configuration options, board specific
  36. */
  37. #ifndef __CONFIG_H
  38. #define __CONFIG_H
  39. /*
  40. * High Level Configuration Options
  41. * (easy to change)
  42. */
  43. #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
  44. #define CONFIG_MBX 1 /* ...on an MBX module */
  45. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  46. #undef CONFIG_8xx_CONS_SMC2
  47. #undef CONFIG_8xx_CONS_NONE
  48. #define CONFIG_BAUDRATE 9600
  49. /* Define this to use the PCI bus */
  50. #undef CONFIG_USE_PCI
  51. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  52. #define CONFIG_8xx_GCLK_FREQ (50000000UL)
  53. #if 1
  54. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  55. #else
  56. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  57. #endif
  58. #define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
  59. #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
  60. "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
  61. "nfsaddrs=10.0.0.99:10.0.0.2"
  62. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  63. #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  64. #undef CONFIG_WATCHDOG /* watchdog disabled */
  65. #define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
  66. CFG_CMD_PCMCIA | CFG_CMD_IDE )
  67. #define CONFIG_DOS_PARTITION
  68. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  69. #include <cmd_confdefs.h>
  70. /*
  71. * Miscellaneous configurable options
  72. */
  73. #define CFG_LONGHELP /* undef to save memory */
  74. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  75. #undef CFG_HUSH_PARSER /* Hush parse for U-Boot */
  76. #ifdef CFG_HUSH_PARSER
  77. #define CFG_PROMPT_HUSH_PS2 "> "
  78. #endif
  79. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  80. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  81. #else
  82. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  83. #endif
  84. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  85. #define CFG_MAXARGS 16 /* max number of command args */
  86. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  87. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  88. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  89. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  90. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  91. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  92. /*
  93. * Low Level Configuration Settings
  94. * (address mappings, register initial values, etc.)
  95. * You should know what you are doing if you make changes here.
  96. */
  97. /*-----------------------------------------------------------------------
  98. * Physical memory map as defined by the MBX PGM
  99. */
  100. #define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
  101. #define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
  102. #define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
  103. #define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
  104. #define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
  105. #define CFG_PCIMEM_OR 0xA0000108
  106. #define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
  107. #define CFG_PCIBRIDGE_OR 0xFFFF0108
  108. /*-----------------------------------------------------------------------
  109. * Definitions for initial stack pointer and data area (in DPRAM)
  110. */
  111. #define CFG_INIT_RAM_ADDR CFG_IMMR
  112. #define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
  113. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  114. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  115. #define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
  116. #define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
  117. #define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
  118. /*-----------------------------------------------------------------------
  119. * Offset in DPMEM where we keep the VPD data
  120. */
  121. #define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000)
  122. /*-----------------------------------------------------------------------
  123. * Start addresses for the final memory configuration
  124. * (Set up by the startup code)
  125. * Please note that CFG_SDRAM_BASE _must_ start at 0
  126. */
  127. #define CFG_SDRAM_BASE 0x00000000
  128. #define CFG_FLASH_BASE 0xfe000000
  129. #ifdef DEBUG
  130. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  131. #else
  132. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  133. #endif
  134. #undef CFG_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
  135. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  136. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  137. /*
  138. * For booting Linux, the board info and command line data
  139. * have to be in the first 8 MB of memory, since this is
  140. * the maximum mapped by the Linux kernel during initialization.
  141. */
  142. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  143. /*-----------------------------------------------------------------------
  144. * FLASH organization
  145. */
  146. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  147. #define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
  148. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  149. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  150. /*-----------------------------------------------------------------------
  151. * NVRAM Configuration
  152. *
  153. * Note: the MBX is special because there is already a firmware on this
  154. * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
  155. * access the NVRAM at the offset 0x1000.
  156. */
  157. #define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
  158. #define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
  159. #define CFG_ENV_SIZE 0x1000
  160. /*-----------------------------------------------------------------------
  161. * Cache Configuration
  162. */
  163. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  164. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  165. #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  166. #endif
  167. /*-----------------------------------------------------------------------
  168. * SYPCR - System Protection Control 11-9
  169. * SYPCR can only be written once after reset!
  170. *-----------------------------------------------------------------------
  171. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  172. */
  173. #if defined(CONFIG_WATCHDOG)
  174. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  175. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  176. #else
  177. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
  178. #endif
  179. /*-----------------------------------------------------------------------
  180. * SIUMCR - SIU Module Configuration 11-6
  181. *-----------------------------------------------------------------------
  182. * PCMCIA config., multi-function pin tri-state
  183. */
  184. /* #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
  185. #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
  186. /*-----------------------------------------------------------------------
  187. * TBSCR - Time Base Status and Control 11-26
  188. *-----------------------------------------------------------------------
  189. * Clear Reference Interrupt Status, Timebase freezing enabled
  190. */
  191. #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  192. /*-----------------------------------------------------------------------
  193. * PISCR - Periodic Interrupt Status and Control 11-31
  194. *-----------------------------------------------------------------------
  195. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  196. */
  197. #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
  198. /*-----------------------------------------------------------------------
  199. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  200. *-----------------------------------------------------------------------
  201. * Reset PLL lock status sticky bit, timer expired status bit and timer
  202. * interrupt status bit - leave PLL multiplication factor unchanged !
  203. */
  204. #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  205. /*-----------------------------------------------------------------------
  206. * SCCR - System Clock and reset Control Register 15-27
  207. *-----------------------------------------------------------------------
  208. * Set clock output, timebase and RTC source and divider,
  209. * power management and some other internal clocks
  210. */
  211. #define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
  212. #define CFG_SCCR SCCR_TBS
  213. /*-----------------------------------------------------------------------
  214. * PCMCIA stuff
  215. *-----------------------------------------------------------------------
  216. *
  217. */
  218. #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  219. #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  220. #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  221. #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  222. #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  223. #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  224. #define CFG_PCMCIA_IO_ADDR (0xEC000000)
  225. #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  226. #define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
  227. #define CONFIG_PCMCIA_SLOT_A 1
  228. /*-----------------------------------------------------------------------
  229. * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  230. *-----------------------------------------------------------------------
  231. */
  232. #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  233. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  234. #undef CONFIG_IDE_LED /* LED for ide not supported */
  235. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  236. #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  237. #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  238. #define CFG_ATA_IDE0_OFFSET 0x0000
  239. #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  240. /* Offset for data I/O */
  241. #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  242. /* Offset for normal register accesses */
  243. #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  244. /* Offset for alternate registers */
  245. #define CFG_ATA_ALT_OFFSET 0x0100
  246. /*-----------------------------------------------------------------------
  247. * Debug Entry Mode
  248. *-----------------------------------------------------------------------
  249. *
  250. */
  251. #define CFG_DER 0
  252. /*
  253. * Internal Definitions
  254. *
  255. * Boot Flags
  256. */
  257. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  258. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  259. #endif /* __CONFIG_H */