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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  4. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  5. * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  6. */
  7. /* U-Boot - Startup Code for PowerPC based Embedded Boards
  8. *
  9. *
  10. * The processor starts at 0x00000100 and the code is executed
  11. * from flash. The code is organized to be at an other address
  12. * in memory, but as long we don't jump around before relocating,
  13. * board_init lies at a quite high address and when the cpu has
  14. * jumped there, everything is ok.
  15. * This works because the cpu gives the FLASH (CS0) the whole
  16. * address space at startup, and board_init lies as a echo of
  17. * the flash somewhere up there in the memory map.
  18. *
  19. * board_init will change CS0 to be positioned at the correct
  20. * address and (s)dram will be positioned at address 0
  21. */
  22. #include <asm-offsets.h>
  23. #include <config.h>
  24. #include <mpc8xx.h>
  25. #include <version.h>
  26. #include <ppc_asm.tmpl>
  27. #include <ppc_defs.h>
  28. #include <asm/cache.h>
  29. #include <asm/mmu.h>
  30. #include <asm/u-boot.h>
  31. /* We don't want the MMU yet.
  32. */
  33. #undef MSR_KERNEL
  34. #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
  35. /*
  36. * Set up GOT: Global Offset Table
  37. *
  38. * Use r12 to access the GOT
  39. */
  40. START_GOT
  41. GOT_ENTRY(_GOT2_TABLE_)
  42. GOT_ENTRY(_FIXUP_TABLE_)
  43. GOT_ENTRY(_start)
  44. GOT_ENTRY(_start_of_vectors)
  45. GOT_ENTRY(_end_of_vectors)
  46. GOT_ENTRY(transfer_to_handler)
  47. GOT_ENTRY(__init_end)
  48. GOT_ENTRY(__bss_end)
  49. GOT_ENTRY(__bss_start)
  50. END_GOT
  51. /*
  52. * r3 - 1st arg to board_init(): IMMP pointer
  53. * r4 - 2nd arg to board_init(): boot flag
  54. */
  55. .text
  56. .long 0x27051956 /* U-Boot Magic Number */
  57. .globl version_string
  58. version_string:
  59. .ascii U_BOOT_VERSION_STRING, "\0"
  60. . = EXC_OFF_SYS_RESET
  61. .globl _start
  62. _start:
  63. lis r3, CONFIG_SYS_IMMR@h /* position IMMR */
  64. mtspr 638, r3
  65. /* Initialize machine status; enable machine check interrupt */
  66. /*----------------------------------------------------------------------*/
  67. li r3, MSR_KERNEL /* Set ME, RI flags */
  68. mtmsr r3
  69. mtspr SRR1, r3 /* Make SRR1 match MSR */
  70. mfspr r3, ICR /* clear Interrupt Cause Register */
  71. /* Initialize debug port registers */
  72. /*----------------------------------------------------------------------*/
  73. xor r0, r0, r0 /* Clear R0 */
  74. mtspr LCTRL1, r0 /* Initialize debug port regs */
  75. mtspr LCTRL2, r0
  76. mtspr COUNTA, r0
  77. mtspr COUNTB, r0
  78. /* Reset the caches */
  79. /*----------------------------------------------------------------------*/
  80. mfspr r3, IC_CST /* Clear error bits */
  81. mfspr r3, DC_CST
  82. lis r3, IDC_UNALL@h /* Unlock all */
  83. mtspr IC_CST, r3
  84. mtspr DC_CST, r3
  85. lis r3, IDC_INVALL@h /* Invalidate all */
  86. mtspr IC_CST, r3
  87. mtspr DC_CST, r3
  88. lis r3, IDC_DISABLE@h /* Disable data cache */
  89. mtspr DC_CST, r3
  90. lis r3, IDC_ENABLE@h /* Enable instruction cache */
  91. mtspr IC_CST, r3
  92. /* invalidate all tlb's */
  93. /*----------------------------------------------------------------------*/
  94. tlbia
  95. isync
  96. /*
  97. * Calculate absolute address in FLASH and jump there
  98. *----------------------------------------------------------------------*/
  99. lis r3, CONFIG_SYS_MONITOR_BASE@h
  100. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  101. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  102. mtlr r3
  103. blr
  104. in_flash:
  105. /* initialize some SPRs that are hard to access from C */
  106. /*----------------------------------------------------------------------*/
  107. /*
  108. * Disable serialized ifetch and show cycles
  109. * (i.e. set processor to normal mode).
  110. * This is also a silicon bug workaround, see errata
  111. */
  112. li r2, 0x0007
  113. mtspr ICTRL, r2
  114. /* Set up debug mode entry */
  115. lis r2, CONFIG_SYS_DER@h
  116. ori r2, r2, CONFIG_SYS_DER@l
  117. mtspr DER, r2
  118. /* set up the stack on top of internal DPRAM */
  119. lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h
  120. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l
  121. stw r0, -4(r3)
  122. stw r0, -8(r3)
  123. addi r1, r3, -8
  124. bl board_init_f_alloc_reserve
  125. addi r1, r3, -8
  126. /* Zeroise the CPM dpram */
  127. lis r4, CONFIG_SYS_IMMR@h
  128. ori r4, r4, (0x2000 - 4)
  129. li r0, (0x2000 / 4)
  130. mtctr r0
  131. li r0, 0
  132. 1: stwu r0, 4(r4)
  133. bdnz 1b
  134. bl board_init_f_init_reserve
  135. /* let the C-code set up the rest */
  136. /* */
  137. /* Be careful to keep code relocatable ! */
  138. /*----------------------------------------------------------------------*/
  139. GET_GOT /* initialize GOT access */
  140. lis r3, CONFIG_SYS_IMMR@h
  141. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  142. bl board_init_f /* run 1st part of board init code (from Flash) */
  143. /* NOTREACHED - board_init_f() does not return */
  144. .globl _start_of_vectors
  145. _start_of_vectors:
  146. /* Machine check */
  147. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  148. /* Data Storage exception. "Never" generated on the 860. */
  149. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  150. /* Instruction Storage exception. "Never" generated on the 860. */
  151. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  152. /* External Interrupt exception. */
  153. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  154. /* Alignment exception. */
  155. . = 0x600
  156. Alignment:
  157. EXCEPTION_PROLOG(SRR0, SRR1)
  158. mfspr r4,DAR
  159. stw r4,_DAR(r21)
  160. mfspr r5,DSISR
  161. stw r5,_DSISR(r21)
  162. addi r3,r1,STACK_FRAME_OVERHEAD
  163. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  164. /* Program check exception */
  165. . = 0x700
  166. ProgramCheck:
  167. EXCEPTION_PROLOG(SRR0, SRR1)
  168. addi r3,r1,STACK_FRAME_OVERHEAD
  169. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  170. MSR_KERNEL, COPY_EE)
  171. /* No FPU on MPC8xx. This exception is not supposed to happen.
  172. */
  173. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  174. /* I guess we could implement decrementer, and may have
  175. * to someday for timekeeping.
  176. */
  177. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  178. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  179. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  180. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  181. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  182. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  183. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  184. /* On the MPC8xx, this is a software emulation interrupt. It occurs
  185. * for all unimplemented and illegal instructions.
  186. */
  187. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  188. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  189. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  190. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  191. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  192. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  193. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  194. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  195. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  196. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  197. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  198. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  199. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  200. STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
  201. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  202. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  203. .globl _end_of_vectors
  204. _end_of_vectors:
  205. . = 0x2000
  206. /*
  207. * This code finishes saving the registers to the exception frame
  208. * and jumps to the appropriate handler for the exception.
  209. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  210. */
  211. .globl transfer_to_handler
  212. transfer_to_handler:
  213. stw r22,_NIP(r21)
  214. lis r22,MSR_POW@h
  215. andc r23,r23,r22
  216. stw r23,_MSR(r21)
  217. SAVE_GPR(7, r21)
  218. SAVE_4GPRS(8, r21)
  219. SAVE_8GPRS(12, r21)
  220. SAVE_8GPRS(24, r21)
  221. mflr r23
  222. andi. r24,r23,0x3f00 /* get vector offset */
  223. stw r24,TRAP(r21)
  224. li r22,0
  225. stw r22,RESULT(r21)
  226. mtspr SPRG2,r22 /* r1 is now kernel sp */
  227. lwz r24,0(r23) /* virtual address of handler */
  228. lwz r23,4(r23) /* where to go when done */
  229. mtspr SRR0,r24
  230. mtspr SRR1,r20
  231. mtlr r23
  232. SYNC
  233. rfi /* jump to handler, enable MMU */
  234. int_return:
  235. mfmsr r28 /* Disable interrupts */
  236. li r4,0
  237. ori r4,r4,MSR_EE
  238. andc r28,r28,r4
  239. SYNC /* Some chip revs need this... */
  240. mtmsr r28
  241. SYNC
  242. lwz r2,_CTR(r1)
  243. lwz r0,_LINK(r1)
  244. mtctr r2
  245. mtlr r0
  246. lwz r2,_XER(r1)
  247. lwz r0,_CCR(r1)
  248. mtspr XER,r2
  249. mtcrf 0xFF,r0
  250. REST_10GPRS(3, r1)
  251. REST_10GPRS(13, r1)
  252. REST_8GPRS(23, r1)
  253. REST_GPR(31, r1)
  254. lwz r2,_NIP(r1) /* Restore environment */
  255. lwz r0,_MSR(r1)
  256. mtspr SRR0,r2
  257. mtspr SRR1,r0
  258. lwz r0,GPR0(r1)
  259. lwz r2,GPR2(r1)
  260. lwz r1,GPR1(r1)
  261. SYNC
  262. rfi
  263. /*------------------------------------------------------------------------------*/
  264. /*
  265. * void relocate_code(addr_sp, gd, addr_moni)
  266. *
  267. * This "function" does not return, instead it continues in RAM
  268. * after relocating the monitor code.
  269. *
  270. * r3 = dest
  271. * r4 = src
  272. * r5 = length in bytes
  273. * r6 = cachelinesize
  274. */
  275. .globl relocate_code
  276. relocate_code:
  277. mr r1, r3 /* Set new stack pointer */
  278. mr r9, r4 /* Save copy of Global Data pointer */
  279. mr r10, r5 /* Save copy of Destination Address */
  280. GET_GOT
  281. mr r3, r5 /* Destination Address */
  282. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  283. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  284. lwz r5, GOT(__init_end)
  285. sub r5, r5, r4
  286. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  287. /*
  288. * Fix GOT pointer:
  289. *
  290. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  291. *
  292. * Offset:
  293. */
  294. sub r15, r10, r4
  295. /* First our own GOT */
  296. add r12, r12, r15
  297. /* then the one used by the C code */
  298. add r30, r30, r15
  299. /*
  300. * Now relocate code
  301. */
  302. cmplw cr1,r3,r4
  303. addi r0,r5,3
  304. srwi. r0,r0,2
  305. beq cr1,4f /* In place copy is not necessary */
  306. beq 7f /* Protect against 0 count */
  307. mtctr r0
  308. bge cr1,2f
  309. la r8,-4(r4)
  310. la r7,-4(r3)
  311. 1: lwzu r0,4(r8)
  312. stwu r0,4(r7)
  313. bdnz 1b
  314. b 4f
  315. 2: slwi r0,r0,2
  316. add r8,r4,r0
  317. add r7,r3,r0
  318. 3: lwzu r0,-4(r8)
  319. stwu r0,-4(r7)
  320. bdnz 3b
  321. /*
  322. * Now flush the cache: note that we must start from a cache aligned
  323. * address. Otherwise we might miss one cache line.
  324. */
  325. 4: cmpwi r6,0
  326. add r5,r3,r5
  327. beq 7f /* Always flush prefetch queue in any case */
  328. subi r0,r6,1
  329. andc r3,r3,r0
  330. mr r4,r3
  331. 5: dcbst 0,r4
  332. add r4,r4,r6
  333. cmplw r4,r5
  334. blt 5b
  335. sync /* Wait for all dcbst to complete on bus */
  336. mr r4,r3
  337. 6: icbi 0,r4
  338. add r4,r4,r6
  339. cmplw r4,r5
  340. blt 6b
  341. 7: sync /* Wait for all icbi to complete on bus */
  342. isync
  343. /*
  344. * We are done. Do not return, instead branch to second part of board
  345. * initialization, now running from RAM.
  346. */
  347. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  348. mtlr r0
  349. blr
  350. in_ram:
  351. /*
  352. * Relocation Function, r12 point to got2+0x8000
  353. *
  354. * Adjust got2 pointers, no need to check for 0, this code
  355. * already puts a few entries in the table.
  356. */
  357. li r0,__got2_entries@sectoff@l
  358. la r3,GOT(_GOT2_TABLE_)
  359. lwz r11,GOT(_GOT2_TABLE_)
  360. mtctr r0
  361. sub r11,r3,r11
  362. addi r3,r3,-4
  363. 1: lwzu r0,4(r3)
  364. cmpwi r0,0
  365. beq- 2f
  366. add r0,r0,r11
  367. stw r0,0(r3)
  368. 2: bdnz 1b
  369. /*
  370. * Now adjust the fixups and the pointers to the fixups
  371. * in case we need to move ourselves again.
  372. */
  373. li r0,__fixup_entries@sectoff@l
  374. lwz r3,GOT(_FIXUP_TABLE_)
  375. cmpwi r0,0
  376. mtctr r0
  377. addi r3,r3,-4
  378. beq 4f
  379. 3: lwzu r4,4(r3)
  380. lwzux r0,r4,r11
  381. cmpwi r0,0
  382. add r0,r0,r11
  383. stw r4,0(r3)
  384. beq- 5f
  385. stw r0,0(r4)
  386. 5: bdnz 3b
  387. 4:
  388. clear_bss:
  389. /*
  390. * Now clear BSS segment
  391. */
  392. lwz r3,GOT(__bss_start)
  393. lwz r4,GOT(__bss_end)
  394. cmplw 0, r3, r4
  395. beq 6f
  396. li r0, 0
  397. 5:
  398. stw r0, 0(r3)
  399. addi r3, r3, 4
  400. cmplw 0, r3, r4
  401. bne 5b
  402. 6:
  403. mr r3, r9 /* Global Data pointer */
  404. mr r4, r10 /* Destination Address */
  405. bl board_init_r
  406. /*
  407. * Copy exception vector code to low memory
  408. *
  409. * r3: dest_addr
  410. * r7: source address, r8: end address, r9: target address
  411. */
  412. .globl trap_init
  413. trap_init:
  414. mflr r4 /* save link register */
  415. GET_GOT
  416. lwz r7, GOT(_start)
  417. lwz r8, GOT(_end_of_vectors)
  418. li r9, 0x100 /* reset vector always at 0x100 */
  419. cmplw 0, r7, r8
  420. bgelr /* return if r7>=r8 - just in case */
  421. 1:
  422. lwz r0, 0(r7)
  423. stw r0, 0(r9)
  424. addi r7, r7, 4
  425. addi r9, r9, 4
  426. cmplw 0, r7, r8
  427. bne 1b
  428. /*
  429. * relocate `hdlr' and `int_return' entries
  430. */
  431. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  432. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  433. 2:
  434. bl trap_reloc
  435. addi r7, r7, 0x100 /* next exception vector */
  436. cmplw 0, r7, r8
  437. blt 2b
  438. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  439. bl trap_reloc
  440. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  441. bl trap_reloc
  442. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  443. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  444. 3:
  445. bl trap_reloc
  446. addi r7, r7, 0x100 /* next exception vector */
  447. cmplw 0, r7, r8
  448. blt 3b
  449. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  450. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  451. 4:
  452. bl trap_reloc
  453. addi r7, r7, 0x100 /* next exception vector */
  454. cmplw 0, r7, r8
  455. blt 4b
  456. mtlr r4 /* restore link register */
  457. blr