interrupts.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. #include <mpc8xx.h>
  9. #include <mpc8xx_irq.h>
  10. #include <time.h>
  11. #include <asm/cpm_8xx.h>
  12. #include <asm/processor.h>
  13. #include <asm/io.h>
  14. #include <asm/ptrace.h>
  15. /************************************************************************/
  16. /*
  17. * CPM interrupt vector functions.
  18. */
  19. struct interrupt_action {
  20. interrupt_handler_t *handler;
  21. void *arg;
  22. };
  23. static struct interrupt_action cpm_vecs[CPMVEC_NR];
  24. static struct interrupt_action irq_vecs[NR_IRQS];
  25. static void cpm_interrupt_init(void);
  26. static void cpm_interrupt(void *regs);
  27. /************************************************************************/
  28. void interrupt_init_cpu(unsigned *decrementer_count)
  29. {
  30. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  31. *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  32. /* disable all interrupts */
  33. out_be32(&immr->im_siu_conf.sc_simask, 0);
  34. /* Configure CPM interrupts */
  35. cpm_interrupt_init();
  36. }
  37. /************************************************************************/
  38. /*
  39. * Handle external interrupts
  40. */
  41. void external_interrupt(struct pt_regs *regs)
  42. {
  43. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  44. int irq;
  45. ulong simask;
  46. ulong vec, v_bit;
  47. /*
  48. * read the SIVEC register and shift the bits down
  49. * to get the irq number
  50. */
  51. vec = in_be32(&immr->im_siu_conf.sc_sivec);
  52. irq = vec >> 26;
  53. v_bit = 0x80000000UL >> irq;
  54. /*
  55. * Read Interrupt Mask Register and Mask Interrupts
  56. */
  57. simask = in_be32(&immr->im_siu_conf.sc_simask);
  58. clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
  59. if (!(irq & 0x1)) { /* External Interrupt ? */
  60. ulong siel;
  61. /*
  62. * Read Interrupt Edge/Level Register
  63. */
  64. siel = in_be32(&immr->im_siu_conf.sc_siel);
  65. if (siel & v_bit) { /* edge triggered interrupt ? */
  66. /*
  67. * Rewrite SIPEND Register to clear interrupt
  68. */
  69. out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
  70. }
  71. }
  72. if (irq_vecs[irq].handler != NULL) {
  73. irq_vecs[irq].handler(irq_vecs[irq].arg);
  74. } else {
  75. printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
  76. irq, vec);
  77. /* turn off the bogus interrupt to avoid it from now */
  78. simask &= ~v_bit;
  79. }
  80. /*
  81. * Re-Enable old Interrupt Mask
  82. */
  83. out_be32(&immr->im_siu_conf.sc_simask, simask);
  84. }
  85. /************************************************************************/
  86. /*
  87. * CPM interrupt handler
  88. */
  89. static void cpm_interrupt(void *regs)
  90. {
  91. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  92. uint vec;
  93. /*
  94. * Get the vector by setting the ACK bit
  95. * and then reading the register.
  96. */
  97. out_be16(&immr->im_cpic.cpic_civr, 1);
  98. vec = in_be16(&immr->im_cpic.cpic_civr);
  99. vec >>= 11;
  100. if (cpm_vecs[vec].handler != NULL) {
  101. (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
  102. } else {
  103. clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
  104. printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
  105. }
  106. /*
  107. * After servicing the interrupt,
  108. * we have to remove the status indicator.
  109. */
  110. setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
  111. }
  112. /*
  113. * The CPM can generate the error interrupt when there is a race
  114. * condition between generating and masking interrupts. All we have
  115. * to do is ACK it and return. This is a no-op function so we don't
  116. * need any special tests in the interrupt handler.
  117. */
  118. static void cpm_error_interrupt(void *dummy)
  119. {
  120. }
  121. /************************************************************************/
  122. /*
  123. * Install and free an interrupt handler
  124. */
  125. void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  126. {
  127. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  128. if ((vec & CPMVEC_OFFSET) != 0) {
  129. /* CPM interrupt */
  130. vec &= 0xffff;
  131. if (cpm_vecs[vec].handler != NULL)
  132. printf("CPM interrupt 0x%x replacing 0x%x\n",
  133. (uint)handler, (uint)cpm_vecs[vec].handler);
  134. cpm_vecs[vec].handler = handler;
  135. cpm_vecs[vec].arg = arg;
  136. setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
  137. } else {
  138. /* SIU interrupt */
  139. if (irq_vecs[vec].handler != NULL)
  140. printf("SIU interrupt %d 0x%x replacing 0x%x\n",
  141. vec, (uint)handler, (uint)cpm_vecs[vec].handler);
  142. irq_vecs[vec].handler = handler;
  143. irq_vecs[vec].arg = arg;
  144. setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
  145. }
  146. }
  147. void irq_free_handler(int vec)
  148. {
  149. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  150. if ((vec & CPMVEC_OFFSET) != 0) {
  151. /* CPM interrupt */
  152. vec &= 0xffff;
  153. clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
  154. cpm_vecs[vec].handler = NULL;
  155. cpm_vecs[vec].arg = NULL;
  156. } else {
  157. /* SIU interrupt */
  158. clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
  159. irq_vecs[vec].handler = NULL;
  160. irq_vecs[vec].arg = NULL;
  161. }
  162. }
  163. /************************************************************************/
  164. static void cpm_interrupt_init(void)
  165. {
  166. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  167. uint cicr;
  168. /*
  169. * Initialize the CPM interrupt controller.
  170. */
  171. cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
  172. ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
  173. out_be32(&immr->im_cpic.cpic_cicr, cicr);
  174. out_be32(&immr->im_cpic.cpic_cimr, 0);
  175. /*
  176. * Install the error handler.
  177. */
  178. irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
  179. setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
  180. /*
  181. * Install the cpm interrupt handler
  182. */
  183. irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
  184. }
  185. /************************************************************************/
  186. /*
  187. * timer_interrupt - gets called when the decrementer overflows,
  188. * with interrupts disabled.
  189. * Trivial implementation - no need to be really accurate.
  190. */
  191. void timer_interrupt_cpu(struct pt_regs *regs)
  192. {
  193. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  194. /* Reset Timer Expired and Timers Interrupt Status */
  195. out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
  196. __asm__ ("nop");
  197. /*
  198. Clear TEXPS (and TMIST on older chips). SPLSS (on older
  199. chips) is cleared too.
  200. Bitwise OR is a read-modify-write operation so ALL bits
  201. which are cleared by writing `1' would be cleared by
  202. operations like
  203. immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
  204. The same can be achieved by simple writing of the PLPRCR
  205. to itself. If a bit value should be preserved, read the
  206. register, ZERO the bit and write, not OR, the result back.
  207. */
  208. setbits_be32(&immr->im_clkrst.car_plprcr, 0);
  209. }
  210. /************************************************************************/