cpu.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
  4. * Jeff Brown
  5. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <time.h>
  11. #include <vsprintf.h>
  12. #include <watchdog.h>
  13. #include <command.h>
  14. #include <asm/cache.h>
  15. #include <asm/mmu.h>
  16. #include <mpc86xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/ppc.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /*
  21. * Default board reset function
  22. */
  23. static void
  24. __board_reset(void)
  25. {
  26. /* Do nothing */
  27. }
  28. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  29. int
  30. checkcpu(void)
  31. {
  32. sys_info_t sysinfo;
  33. uint pvr, svr;
  34. uint major, minor;
  35. char buf1[32], buf2[32];
  36. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  37. volatile ccsr_gur_t *gur = &immap->im_gur;
  38. struct cpu_type *cpu;
  39. uint msscr0 = mfspr(MSSCR0);
  40. svr = get_svr();
  41. major = SVR_MAJ(svr);
  42. minor = SVR_MIN(svr);
  43. if (cpu_numcores() > 1) {
  44. #ifndef CONFIG_MP
  45. puts("Unicore software on multiprocessor system!!\n"
  46. "To enable mutlticore build define CONFIG_MP\n");
  47. #endif
  48. }
  49. puts("CPU: ");
  50. cpu = gd->arch.cpu;
  51. puts(cpu->name);
  52. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  53. puts("Core: ");
  54. pvr = get_pvr();
  55. major = PVR_E600_MAJ(pvr);
  56. minor = PVR_E600_MIN(pvr);
  57. printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
  58. if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
  59. puts("\n Core1Translation Enabled");
  60. debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
  61. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  62. get_sys_info(&sysinfo);
  63. puts("Clock Configuration:\n");
  64. printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
  65. printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  66. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  67. strmhz(buf1, sysinfo.freq_systembus / 2),
  68. strmhz(buf2, sysinfo.freq_systembus));
  69. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  70. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  71. } else {
  72. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  73. sysinfo.freq_localbus);
  74. }
  75. puts("L1: D-cache 32 KiB enabled\n");
  76. puts(" I-cache 32 KiB enabled\n");
  77. puts("L2: ");
  78. if (get_l2cr() & 0x80000000) {
  79. #if defined(CONFIG_ARCH_MPC8610)
  80. puts("256");
  81. #elif defined(CONFIG_ARCH_MPC8641)
  82. puts("512");
  83. #endif
  84. puts(" KiB enabled\n");
  85. } else {
  86. puts("Disabled\n");
  87. }
  88. return 0;
  89. }
  90. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  91. {
  92. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  93. volatile ccsr_gur_t *gur = &immap->im_gur;
  94. /* Attempt board-specific reset */
  95. board_reset();
  96. /* Next try asserting HRESET_REQ */
  97. out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
  98. while (1)
  99. ;
  100. return 1;
  101. }
  102. /*
  103. * Get timebase clock frequency
  104. */
  105. unsigned long
  106. get_tbclk(void)
  107. {
  108. sys_info_t sys_info;
  109. get_sys_info(&sys_info);
  110. return (sys_info.freq_systembus + 3L) / 4L;
  111. }
  112. #if defined(CONFIG_WATCHDOG)
  113. void
  114. watchdog_reset(void)
  115. {
  116. #if defined(CONFIG_ARCH_MPC8610)
  117. /*
  118. * This actually feed the hard enabled watchdog.
  119. */
  120. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  121. volatile ccsr_wdt_t *wdt = &immap->im_wdt;
  122. volatile ccsr_gur_t *gur = &immap->im_gur;
  123. u32 tmp = gur->pordevsr;
  124. if (tmp & 0x4000) {
  125. wdt->swsrr = 0x556c;
  126. wdt->swsrr = 0xaa39;
  127. }
  128. #endif
  129. }
  130. #endif /* CONFIG_WATCHDOG */
  131. /*
  132. * Print out the state of various machine registers.
  133. * Currently prints out LAWs, BR0/OR0, and BATs
  134. */
  135. void print_reginfo(void)
  136. {
  137. print_bats();
  138. print_laws();
  139. print_lbc_regs();
  140. }
  141. /*
  142. * Set the DDR BATs to reflect the actual size of DDR.
  143. *
  144. * dram_size is the actual size of DDR, in bytes
  145. *
  146. * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
  147. * are using a single BAT to cover DDR.
  148. *
  149. * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
  150. * is not defined) then we might have a situation where U-Boot will attempt
  151. * to relocated itself outside of the region mapped by DBAT0.
  152. * This will cause a machine check.
  153. *
  154. * Currently we are limited to power of two sized DDR since we only use a
  155. * single bat. If a non-power of two size is used that is less than
  156. * CONFIG_MAX_MEM_MAPPED u-boot will crash.
  157. *
  158. */
  159. void setup_ddr_bat(phys_addr_t dram_size)
  160. {
  161. unsigned long batu, bl;
  162. bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
  163. if (BATU_SIZE(bl) != dram_size) {
  164. u64 sz = (u64)dram_size - BATU_SIZE(bl);
  165. print_size(sz, " left unmapped\n");
  166. }
  167. batu = bl | BATU_VS | BATU_VP;
  168. write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
  169. write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
  170. }