cache_init.S 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Cache-handling routined for MIPS CPUs
  4. *
  5. * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  6. */
  7. #include <asm-offsets.h>
  8. #include <config.h>
  9. #include <asm/asm.h>
  10. #include <asm/regdef.h>
  11. #include <asm/mipsregs.h>
  12. #include <asm/addrspace.h>
  13. #include <asm/cacheops.h>
  14. #include <asm/cm.h>
  15. .macro f_fill64 dst, offset, val
  16. LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
  17. LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
  18. LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
  19. LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
  20. LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
  21. LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
  22. LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
  23. LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
  24. #if LONGSIZE == 4
  25. LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
  26. LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
  27. LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
  28. LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
  29. LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
  30. LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
  31. LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
  32. LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
  33. #endif
  34. .endm
  35. .macro cache_loop curr, end, line_sz, op
  36. 10: cache \op, 0(\curr)
  37. PTR_ADDU \curr, \curr, \line_sz
  38. bne \curr, \end, 10b
  39. .endm
  40. .macro l1_info sz, line_sz, off
  41. .set push
  42. .set noat
  43. mfc0 $1, CP0_CONFIG, 1
  44. /* detect line size */
  45. srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
  46. andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
  47. move \sz, zero
  48. beqz \line_sz, 10f
  49. li \sz, 2
  50. sllv \line_sz, \sz, \line_sz
  51. /* detect associativity */
  52. srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
  53. andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
  54. addiu \sz, \sz, 1
  55. /* sz *= line_sz */
  56. mul \sz, \sz, \line_sz
  57. /* detect log32(sets) */
  58. srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
  59. andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
  60. addiu $1, $1, 1
  61. andi $1, $1, 0x7
  62. /* sz <<= log32(sets) */
  63. sllv \sz, \sz, $1
  64. /* sz *= 32 */
  65. li $1, 32
  66. mul \sz, \sz, $1
  67. 10:
  68. .set pop
  69. .endm
  70. /*
  71. * The changing of Kernel mode cacheability must be done from KSEG1.
  72. * If the code is executing from KSEG0, jump to KSEG1 during the execution
  73. * of change_k0_cca. change_k0_cca itself clears all hazards when returning.
  74. */
  75. .macro change_k0_cca_kseg1 mode
  76. PTR_LA t0, change_k0_cca
  77. li t1, CPHYSADDR(~0)
  78. and t0, t0, t1
  79. PTR_LI t1, CKSEG1
  80. or t0, t0, t1
  81. li a0, \mode
  82. jalr t0
  83. .endm
  84. /*
  85. * mips_cache_reset - low level initialisation of the primary caches
  86. *
  87. * This routine initialises the primary caches to ensure that they have good
  88. * parity. It must be called by the ROM before any cached locations are used
  89. * to prevent the possibility of data with bad parity being written to memory.
  90. *
  91. * To initialise the instruction cache it is essential that a source of data
  92. * with good parity is available. This routine will initialise an area of
  93. * memory starting at location zero to be used as a source of parity.
  94. *
  95. * Note that this function does not follow the standard calling convention &
  96. * may clobber typically callee-saved registers.
  97. *
  98. * RETURNS: N/A
  99. *
  100. */
  101. #define R_RETURN s0
  102. #define R_IC_SIZE s1
  103. #define R_IC_LINE s2
  104. #define R_DC_SIZE s3
  105. #define R_DC_LINE s4
  106. #define R_L2_SIZE s5
  107. #define R_L2_LINE s6
  108. #define R_L2_BYPASSED s7
  109. #define R_L2_L2C t8
  110. LEAF(mips_cache_reset)
  111. move R_RETURN, ra
  112. #ifdef CONFIG_MIPS_L2_CACHE
  113. /*
  114. * For there to be an L2 present, Config2 must be present. If it isn't
  115. * then we proceed knowing there's no L2 cache.
  116. */
  117. move R_L2_SIZE, zero
  118. move R_L2_LINE, zero
  119. move R_L2_BYPASSED, zero
  120. move R_L2_L2C, zero
  121. mfc0 t0, CP0_CONFIG, 1
  122. bgez t0, l2_probe_done
  123. /*
  124. * From MIPSr6 onwards the L2 cache configuration might not be reported
  125. * by Config2. The Config5.L2C bit indicates whether this is the case,
  126. * and if it is then we need knowledge of where else to look. For cores
  127. * from Imagination Technologies this is a CM GCR.
  128. */
  129. # if __mips_isa_rev >= 6
  130. /* Check that Config5 exists */
  131. mfc0 t0, CP0_CONFIG, 2
  132. bgez t0, l2_probe_cop0
  133. mfc0 t0, CP0_CONFIG, 3
  134. bgez t0, l2_probe_cop0
  135. mfc0 t0, CP0_CONFIG, 4
  136. bgez t0, l2_probe_cop0
  137. /* Check Config5.L2C is set */
  138. mfc0 t0, CP0_CONFIG, 5
  139. and R_L2_L2C, t0, MIPS_CONF5_L2C
  140. beqz R_L2_L2C, l2_probe_cop0
  141. /* Config5.L2C is set */
  142. # ifdef CONFIG_MIPS_CM
  143. /* The CM will provide L2 configuration */
  144. PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
  145. lw t1, GCR_L2_CONFIG(t0)
  146. bgez t1, l2_probe_done
  147. ext R_L2_LINE, t1, \
  148. GCR_L2_CONFIG_LINESZ_SHIFT, GCR_L2_CONFIG_LINESZ_BITS
  149. beqz R_L2_LINE, l2_probe_done
  150. li t2, 2
  151. sllv R_L2_LINE, t2, R_L2_LINE
  152. ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
  153. addiu t2, t2, 1
  154. mul R_L2_SIZE, R_L2_LINE, t2
  155. ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
  156. sllv R_L2_SIZE, R_L2_SIZE, t2
  157. li t2, 64
  158. mul R_L2_SIZE, R_L2_SIZE, t2
  159. /* Bypass the L2 cache so that we can init the L1s early */
  160. or t1, t1, GCR_L2_CONFIG_BYPASS
  161. sw t1, GCR_L2_CONFIG(t0)
  162. sync
  163. li R_L2_BYPASSED, 1
  164. /* Zero the L2 tag registers */
  165. sw zero, GCR_L2_TAG_ADDR(t0)
  166. sw zero, GCR_L2_TAG_ADDR_UPPER(t0)
  167. sw zero, GCR_L2_TAG_STATE(t0)
  168. sw zero, GCR_L2_TAG_STATE_UPPER(t0)
  169. sw zero, GCR_L2_DATA(t0)
  170. sw zero, GCR_L2_DATA_UPPER(t0)
  171. sync
  172. # else
  173. /* We don't know how to retrieve L2 configuration on this system */
  174. # endif
  175. b l2_probe_done
  176. # endif
  177. /*
  178. * For pre-r6 systems, or r6 systems with Config5.L2C==0, probe the L2
  179. * cache configuration from the cop0 Config2 register.
  180. */
  181. l2_probe_cop0:
  182. mfc0 t0, CP0_CONFIG, 2
  183. srl R_L2_LINE, t0, MIPS_CONF2_SL_SHF
  184. andi R_L2_LINE, R_L2_LINE, MIPS_CONF2_SL >> MIPS_CONF2_SL_SHF
  185. beqz R_L2_LINE, l2_probe_done
  186. li t1, 2
  187. sllv R_L2_LINE, t1, R_L2_LINE
  188. srl t1, t0, MIPS_CONF2_SA_SHF
  189. andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF
  190. addiu t1, t1, 1
  191. mul R_L2_SIZE, R_L2_LINE, t1
  192. srl t1, t0, MIPS_CONF2_SS_SHF
  193. andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF
  194. sllv R_L2_SIZE, R_L2_SIZE, t1
  195. li t1, 64
  196. mul R_L2_SIZE, R_L2_SIZE, t1
  197. /* Attempt to bypass the L2 so that we can init the L1s early */
  198. or t0, t0, MIPS_CONF2_L2B
  199. mtc0 t0, CP0_CONFIG, 2
  200. ehb
  201. mfc0 t0, CP0_CONFIG, 2
  202. and R_L2_BYPASSED, t0, MIPS_CONF2_L2B
  203. /* Zero the L2 tag registers */
  204. mtc0 zero, CP0_TAGLO, 4
  205. ehb
  206. l2_probe_done:
  207. #endif
  208. #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
  209. li R_IC_SIZE, CONFIG_SYS_ICACHE_SIZE
  210. li R_IC_LINE, CONFIG_SYS_ICACHE_LINE_SIZE
  211. #else
  212. l1_info R_IC_SIZE, R_IC_LINE, MIPS_CONF1_IA_SHF
  213. #endif
  214. #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
  215. li R_DC_SIZE, CONFIG_SYS_DCACHE_SIZE
  216. li R_DC_LINE, CONFIG_SYS_DCACHE_LINE_SIZE
  217. #else
  218. l1_info R_DC_SIZE, R_DC_LINE, MIPS_CONF1_DA_SHF
  219. #endif
  220. #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
  221. /* Determine the largest L1 cache size */
  222. #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
  223. #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
  224. li v0, CONFIG_SYS_ICACHE_SIZE
  225. #else
  226. li v0, CONFIG_SYS_DCACHE_SIZE
  227. #endif
  228. #else
  229. move v0, R_IC_SIZE
  230. sltu t1, R_IC_SIZE, R_DC_SIZE
  231. movn v0, R_DC_SIZE, t1
  232. #endif
  233. /*
  234. * Now clear that much memory starting from zero.
  235. */
  236. PTR_LI a0, CKSEG1ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  237. PTR_ADDU a1, a0, v0
  238. 2: PTR_ADDIU a0, 64
  239. f_fill64 a0, -64, zero
  240. bne a0, a1, 2b
  241. #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
  242. #ifdef CONFIG_MIPS_L2_CACHE
  243. /*
  244. * If the L2 is bypassed, init the L1 first so that we can execute the
  245. * rest of the cache initialisation using the L1 instruction cache.
  246. */
  247. bnez R_L2_BYPASSED, l1_init
  248. l2_init:
  249. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  250. PTR_ADDU t1, t0, R_L2_SIZE
  251. 1: cache INDEX_STORE_TAG_SD, 0(t0)
  252. PTR_ADDU t0, t0, R_L2_LINE
  253. bne t0, t1, 1b
  254. /*
  255. * If the L2 was bypassed then we already initialised the L1s before
  256. * the L2, so we are now done.
  257. */
  258. bnez R_L2_BYPASSED, l2_unbypass
  259. #endif
  260. /*
  261. * The TagLo registers used depend upon the CPU implementation, but the
  262. * architecture requires that it is safe for software to write to both
  263. * TagLo selects 0 & 2 covering supported cases.
  264. */
  265. l1_init:
  266. mtc0 zero, CP0_TAGLO
  267. mtc0 zero, CP0_TAGLO, 2
  268. ehb
  269. /*
  270. * The caches are probably in an indeterminate state, so we force good
  271. * parity into them by doing an invalidate for each line. If
  272. * CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
  273. * perform a load/fill & a further invalidate for each line, assuming
  274. * that the bottom of RAM (having just been cleared) will generate good
  275. * parity for the cache.
  276. */
  277. /*
  278. * Initialize the I-cache first,
  279. */
  280. blez R_IC_SIZE, 1f
  281. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  282. PTR_ADDU t1, t0, R_IC_SIZE
  283. /* clear tag to invalidate */
  284. cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
  285. #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
  286. /* fill once, so data field parity is correct */
  287. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  288. cache_loop t0, t1, R_IC_LINE, FILL
  289. /* invalidate again - prudent but not strictly neccessary */
  290. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  291. cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
  292. #endif
  293. sync
  294. /*
  295. * Enable use of the I-cache by setting Config.K0.
  296. */
  297. change_k0_cca_kseg1 CONF_CM_CACHABLE_NONCOHERENT
  298. /*
  299. * then initialize D-cache.
  300. */
  301. 1: blez R_DC_SIZE, 3f
  302. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  303. PTR_ADDU t1, t0, R_DC_SIZE
  304. /* clear all tags */
  305. cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
  306. #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
  307. /* load from each line (in cached space) */
  308. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  309. 2: LONG_L zero, 0(t0)
  310. PTR_ADDU t0, R_DC_LINE
  311. bne t0, t1, 2b
  312. /* clear all tags */
  313. PTR_LI t0, CKSEG0ADDR(CONFIG_MIPS_CACHE_INDEX_BASE)
  314. cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
  315. #endif
  316. 3:
  317. #ifdef CONFIG_MIPS_L2_CACHE
  318. /* If the L2 isn't bypassed then we're done */
  319. beqz R_L2_BYPASSED, return
  320. /* The L2 is bypassed - go initialise it */
  321. b l2_init
  322. l2_unbypass:
  323. # if __mips_isa_rev >= 6
  324. beqz R_L2_L2C, 1f
  325. li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
  326. lw t1, GCR_L2_CONFIG(t0)
  327. xor t1, t1, GCR_L2_CONFIG_BYPASS
  328. sw t1, GCR_L2_CONFIG(t0)
  329. sync
  330. ehb
  331. b 2f
  332. # endif
  333. 1: mfc0 t0, CP0_CONFIG, 2
  334. xor t0, t0, MIPS_CONF2_L2B
  335. mtc0 t0, CP0_CONFIG, 2
  336. ehb
  337. 2:
  338. # ifdef CONFIG_MIPS_CM
  339. /* Config3 must exist for a CM to be present */
  340. mfc0 t0, CP0_CONFIG, 1
  341. bgez t0, 2f
  342. mfc0 t0, CP0_CONFIG, 2
  343. bgez t0, 2f
  344. /* Check Config3.CMGCR to determine CM presence */
  345. mfc0 t0, CP0_CONFIG, 3
  346. and t0, t0, MIPS_CONF3_CMGCR
  347. beqz t0, 2f
  348. /* Change Config.K0 to a coherent CCA */
  349. change_k0_cca_kseg1 CONF_CM_CACHABLE_COW
  350. /*
  351. * Join the coherent domain such that the caches of this core are kept
  352. * coherent with those of other cores.
  353. */
  354. PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
  355. lw t1, GCR_REV(t0)
  356. li t2, GCR_REV_CM3
  357. li t3, GCR_Cx_COHERENCE_EN
  358. bge t1, t2, 1f
  359. li t3, GCR_Cx_COHERENCE_DOM_EN
  360. 1: sw t3, GCR_Cx_COHERENCE(t0)
  361. ehb
  362. 2:
  363. # endif
  364. #endif
  365. return:
  366. /* Ensure all cache operations complete before returning */
  367. sync
  368. jr R_RETURN
  369. END(mips_cache_reset)
  370. LEAF(mips_cache_disable)
  371. move R_RETURN, ra
  372. change_k0_cca_kseg1 CONF_CM_UNCACHED
  373. jr R_RETURN
  374. END(mips_cache_disable)
  375. LEAF(change_k0_cca)
  376. mfc0 t0, CP0_CONFIG
  377. #if __mips_isa_rev >= 2
  378. ins t0, a0, 0, 3
  379. #else
  380. xor a0, a0, t0
  381. andi a0, a0, CONF_CM_CMASK
  382. xor a0, a0, t0
  383. #endif
  384. mtc0 a0, CP0_CONFIG
  385. jr.hb ra
  386. END(change_k0_cca)