clk_ccf.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <asm/clk.h>
  10. #include <dm/test.h>
  11. #include <dm/uclass.h>
  12. #include <linux/err.h>
  13. #include <test/test.h>
  14. #include <test/ut.h>
  15. #include <sandbox-clk.h>
  16. /* Tests for Common Clock Framework driver */
  17. static int dm_test_clk_ccf(struct unit_test_state *uts)
  18. {
  19. struct clk *clk, *pclk;
  20. struct udevice *dev;
  21. long long rate;
  22. int ret;
  23. /* Get the device using the clk device */
  24. ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
  25. /* Test for clk_get_by_id() */
  26. ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
  27. ut_assertok(ret);
  28. ut_asserteq_str("ecspi_root", clk->dev->name);
  29. /* Test for clk_get_parent_rate() */
  30. ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
  31. ut_assertok(ret);
  32. ut_asserteq_str("ecspi1", clk->dev->name);
  33. rate = clk_get_parent_rate(clk);
  34. ut_asserteq(rate, 20000000);
  35. /* Test the mux of CCF */
  36. ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
  37. ut_assertok(ret);
  38. ut_asserteq_str("usdhc1_sel", clk->dev->name);
  39. rate = clk_get_parent_rate(clk);
  40. ut_asserteq(rate, 60000000);
  41. ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
  42. ut_assertok(ret);
  43. ut_asserteq_str("usdhc2_sel", clk->dev->name);
  44. rate = clk_get_parent_rate(clk);
  45. ut_asserteq(rate, 80000000);
  46. pclk = clk_get_parent(clk);
  47. ut_asserteq_str("pll3_80m", pclk->dev->name);
  48. /* Test the composite of CCF */
  49. ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
  50. ut_assertok(ret);
  51. ut_asserteq_str("i2c", clk->dev->name);
  52. rate = clk_get_rate(clk);
  53. ut_asserteq(rate, 60000000);
  54. #if CONFIG_IS_ENABLED(CLK_CCF)
  55. /* Test clk tree enable/disable */
  56. ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
  57. ut_assertok(ret);
  58. ut_asserteq_str("i2c_root", clk->dev->name);
  59. ret = clk_enable(clk);
  60. ut_assertok(ret);
  61. ret = sandbox_clk_enable_count(clk);
  62. ut_asserteq(ret, 1);
  63. ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
  64. ut_assertok(ret);
  65. ret = sandbox_clk_enable_count(pclk);
  66. ut_asserteq(ret, 1);
  67. ret = clk_disable(clk);
  68. ut_assertok(ret);
  69. ret = sandbox_clk_enable_count(clk);
  70. ut_asserteq(ret, 0);
  71. ret = sandbox_clk_enable_count(pclk);
  72. ut_asserteq(ret, 0);
  73. #endif
  74. return 1;
  75. }
  76. DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);