zynqmp.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cpu_func.h>
  9. #include <debug_uart.h>
  10. #include <env.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <net.h>
  14. #include <sata.h>
  15. #include <ahci.h>
  16. #include <scsi.h>
  17. #include <malloc.h>
  18. #include <wdt.h>
  19. #include <asm/arch/clk.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/psu_init_gpl.h>
  23. #include <asm/cache.h>
  24. #include <asm/io.h>
  25. #include <asm/ptrace.h>
  26. #include <dm/device.h>
  27. #include <dm/uclass.h>
  28. #include <usb.h>
  29. #include <dwc3-uboot.h>
  30. #include <zynqmppl.h>
  31. #include <zynqmp_firmware.h>
  32. #include <g_dnl.h>
  33. #include <linux/bitops.h>
  34. #include <linux/delay.h>
  35. #include <linux/sizes.h>
  36. #include "../common/board.h"
  37. #include "pm_cfg_obj.h"
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  40. !defined(CONFIG_SPL_BUILD)
  41. static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  42. static const struct {
  43. u32 id;
  44. u32 ver;
  45. char *name;
  46. bool evexists;
  47. } zynqmp_devices[] = {
  48. {
  49. .id = 0x10,
  50. .name = "3eg",
  51. },
  52. {
  53. .id = 0x10,
  54. .ver = 0x2c,
  55. .name = "3cg",
  56. },
  57. {
  58. .id = 0x11,
  59. .name = "2eg",
  60. },
  61. {
  62. .id = 0x11,
  63. .ver = 0x2c,
  64. .name = "2cg",
  65. },
  66. {
  67. .id = 0x20,
  68. .name = "5ev",
  69. .evexists = 1,
  70. },
  71. {
  72. .id = 0x20,
  73. .ver = 0x100,
  74. .name = "5eg",
  75. .evexists = 1,
  76. },
  77. {
  78. .id = 0x20,
  79. .ver = 0x12c,
  80. .name = "5cg",
  81. .evexists = 1,
  82. },
  83. {
  84. .id = 0x21,
  85. .name = "4ev",
  86. .evexists = 1,
  87. },
  88. {
  89. .id = 0x21,
  90. .ver = 0x100,
  91. .name = "4eg",
  92. .evexists = 1,
  93. },
  94. {
  95. .id = 0x21,
  96. .ver = 0x12c,
  97. .name = "4cg",
  98. .evexists = 1,
  99. },
  100. {
  101. .id = 0x30,
  102. .name = "7ev",
  103. .evexists = 1,
  104. },
  105. {
  106. .id = 0x30,
  107. .ver = 0x100,
  108. .name = "7eg",
  109. .evexists = 1,
  110. },
  111. {
  112. .id = 0x30,
  113. .ver = 0x12c,
  114. .name = "7cg",
  115. .evexists = 1,
  116. },
  117. {
  118. .id = 0x38,
  119. .name = "9eg",
  120. },
  121. {
  122. .id = 0x38,
  123. .ver = 0x2c,
  124. .name = "9cg",
  125. },
  126. {
  127. .id = 0x39,
  128. .name = "6eg",
  129. },
  130. {
  131. .id = 0x39,
  132. .ver = 0x2c,
  133. .name = "6cg",
  134. },
  135. {
  136. .id = 0x40,
  137. .name = "11eg",
  138. },
  139. { /* For testing purpose only */
  140. .id = 0x50,
  141. .ver = 0x2c,
  142. .name = "15cg",
  143. },
  144. {
  145. .id = 0x50,
  146. .name = "15eg",
  147. },
  148. {
  149. .id = 0x58,
  150. .name = "19eg",
  151. },
  152. {
  153. .id = 0x59,
  154. .name = "17eg",
  155. },
  156. {
  157. .id = 0x61,
  158. .name = "21dr",
  159. },
  160. {
  161. .id = 0x63,
  162. .name = "23dr",
  163. },
  164. {
  165. .id = 0x65,
  166. .name = "25dr",
  167. },
  168. {
  169. .id = 0x64,
  170. .name = "27dr",
  171. },
  172. {
  173. .id = 0x60,
  174. .name = "28dr",
  175. },
  176. {
  177. .id = 0x62,
  178. .name = "29dr",
  179. },
  180. {
  181. .id = 0x66,
  182. .name = "39dr",
  183. },
  184. {
  185. .id = 0x7b,
  186. .name = "48dr",
  187. },
  188. {
  189. .id = 0x7e,
  190. .name = "49dr",
  191. },
  192. };
  193. #endif
  194. #define ZYNQMP_VERSION_SIZE 9
  195. #define ZYNQMP_PL_STATUS_BIT 9
  196. #define ZYNQMP_IPDIS_VCU_BIT 8
  197. #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
  198. #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
  199. #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
  200. ~BIT(ZYNQMP_IPDIS_VCU_BIT)
  201. #define MAX_VARIANTS_EV 3
  202. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  203. !defined(CONFIG_SPL_BUILD)
  204. static char *zynqmp_get_silicon_idcode_name(void)
  205. {
  206. u32 i, id, ver, j;
  207. char *buf;
  208. static char name[ZYNQMP_VERSION_SIZE];
  209. u32 ret_payload[PAYLOAD_ARG_CNT];
  210. xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
  211. /*
  212. * Firmware returns:
  213. * payload[0][31:0] = status of the operation
  214. * payload[1]] = IDCODE
  215. * payload[2][19:0] = Version
  216. * payload[2][28:20] = EXTENDED_IDCODE
  217. * payload[2][29] = PL_INIT
  218. */
  219. /* Get IDCODE field */
  220. id = ret_payload[1];
  221. id &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK;
  222. id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  223. /* Shift silicon version info */
  224. ver = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
  225. debug("%s, ID: 0x%0X, Ver: 0x%0X\r\n", __func__, id, ver);
  226. for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
  227. if (zynqmp_devices[i].id == id) {
  228. if (zynqmp_devices[i].evexists &&
  229. !(ver & ZYNQMP_PL_STATUS_MASK))
  230. break;
  231. if (zynqmp_devices[i].ver == (ver &
  232. ZYNQMP_CSU_VERSION_MASK))
  233. break;
  234. }
  235. }
  236. if (i >= ARRAY_SIZE(zynqmp_devices))
  237. return "unknown";
  238. strncat(name, "zu", 2);
  239. if (!zynqmp_devices[i].evexists ||
  240. (ver & ZYNQMP_PL_STATUS_MASK)) {
  241. strncat(name, zynqmp_devices[i].name,
  242. ZYNQMP_VERSION_SIZE - 3);
  243. return name;
  244. }
  245. /*
  246. * Here we are means, PL not powered up and ev variant
  247. * exists. So, we need to ignore VCU disable bit(8) in
  248. * version and findout if its CG or EG/EV variant.
  249. */
  250. for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
  251. if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
  252. (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
  253. strncat(name, zynqmp_devices[i].name,
  254. ZYNQMP_VERSION_SIZE - 3);
  255. break;
  256. }
  257. }
  258. if (j >= MAX_VARIANTS_EV)
  259. return "unknown";
  260. if (strstr(name, "eg") || strstr(name, "ev")) {
  261. buf = strstr(name, "e");
  262. *buf = '\0';
  263. }
  264. return name;
  265. }
  266. #endif
  267. int board_early_init_f(void)
  268. {
  269. #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
  270. int ret;
  271. ret = psu_init();
  272. if (ret)
  273. return ret;
  274. /* Delay is required for clocks to be propagated */
  275. udelay(1000000);
  276. #endif
  277. #ifdef CONFIG_DEBUG_UART
  278. /* Uart debug for sure */
  279. debug_uart_init();
  280. puts("Debug uart enabled\n"); /* or printch() */
  281. #endif
  282. return 0;
  283. }
  284. static int multi_boot(void)
  285. {
  286. u32 multiboot;
  287. multiboot = readl(&csu_base->multi_boot);
  288. printf("Multiboot:\t%d\n", multiboot);
  289. return 0;
  290. }
  291. #define PS_SYSMON_ANALOG_BUS_VAL 0x3210
  292. #define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
  293. int board_init(void)
  294. {
  295. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  296. struct udevice *dev;
  297. uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
  298. if (!dev)
  299. panic("PMU Firmware device not found - Enable it");
  300. #endif
  301. #if defined(CONFIG_SPL_BUILD)
  302. /* Check *at build time* if the filename is an non-empty string */
  303. if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
  304. zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
  305. zynqmp_pm_cfg_obj_size);
  306. #endif
  307. printf("EL Level:\tEL%d\n", current_el());
  308. /* Bug in ROM sets wrong value in this register */
  309. writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
  310. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  311. !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
  312. defined(CONFIG_SPL_BUILD))
  313. zynqmppl.name = zynqmp_get_silicon_idcode_name();
  314. printf("Chip ID:\t%s\n", zynqmppl.name);
  315. fpga_init();
  316. fpga_add(fpga_xilinx, &zynqmppl);
  317. #endif
  318. if (current_el() == 3)
  319. multi_boot();
  320. return 0;
  321. }
  322. int board_early_init_r(void)
  323. {
  324. u32 val;
  325. if (current_el() != 3)
  326. return 0;
  327. val = readl(&crlapb_base->timestamp_ref_ctrl);
  328. val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  329. if (!val) {
  330. val = readl(&crlapb_base->timestamp_ref_ctrl);
  331. val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  332. writel(val, &crlapb_base->timestamp_ref_ctrl);
  333. /* Program freq register in System counter */
  334. writel(zynqmp_get_system_timer_freq(),
  335. &iou_scntr_secure->base_frequency_id_register);
  336. /* And enable system counter */
  337. writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  338. &iou_scntr_secure->counter_control_register);
  339. }
  340. return 0;
  341. }
  342. unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
  343. char *const argv[])
  344. {
  345. int ret = 0;
  346. if (current_el() > 1) {
  347. smp_kick_all_cpus();
  348. dcache_disable();
  349. armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
  350. ES_TO_AARCH64);
  351. } else {
  352. printf("FAIL: current EL is not above EL1\n");
  353. ret = EINVAL;
  354. }
  355. return ret;
  356. }
  357. #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
  358. int dram_init_banksize(void)
  359. {
  360. int ret;
  361. ret = fdtdec_setup_memory_banksize();
  362. if (ret)
  363. return ret;
  364. mem_map_fill();
  365. return 0;
  366. }
  367. int dram_init(void)
  368. {
  369. if (fdtdec_setup_mem_size_base() != 0)
  370. return -EINVAL;
  371. return 0;
  372. }
  373. #else
  374. int dram_init_banksize(void)
  375. {
  376. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  377. gd->bd->bi_dram[0].size = get_effective_memsize();
  378. mem_map_fill();
  379. return 0;
  380. }
  381. int dram_init(void)
  382. {
  383. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  384. CONFIG_SYS_SDRAM_SIZE);
  385. return 0;
  386. }
  387. #endif
  388. void reset_cpu(ulong addr)
  389. {
  390. }
  391. #if defined(CONFIG_BOARD_LATE_INIT)
  392. static const struct {
  393. u32 bit;
  394. const char *name;
  395. } reset_reasons[] = {
  396. { RESET_REASON_DEBUG_SYS, "DEBUG" },
  397. { RESET_REASON_SOFT, "SOFT" },
  398. { RESET_REASON_SRST, "SRST" },
  399. { RESET_REASON_PSONLY, "PS-ONLY" },
  400. { RESET_REASON_PMU, "PMU" },
  401. { RESET_REASON_INTERNAL, "INTERNAL" },
  402. { RESET_REASON_EXTERNAL, "EXTERNAL" },
  403. {}
  404. };
  405. static int reset_reason(void)
  406. {
  407. u32 reg;
  408. int i, ret;
  409. const char *reason = NULL;
  410. ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
  411. if (ret)
  412. return -EINVAL;
  413. puts("Reset reason:\t");
  414. for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
  415. if (reg & reset_reasons[i].bit) {
  416. reason = reset_reasons[i].name;
  417. printf("%s ", reset_reasons[i].name);
  418. break;
  419. }
  420. }
  421. puts("\n");
  422. env_set("reset_reason", reason);
  423. ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
  424. if (ret)
  425. return -EINVAL;
  426. return ret;
  427. }
  428. static int set_fdtfile(void)
  429. {
  430. char *compatible, *fdtfile;
  431. const char *suffix = ".dtb";
  432. const char *vendor = "xilinx/";
  433. int fdt_compat_len;
  434. if (env_get("fdtfile"))
  435. return 0;
  436. compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
  437. &fdt_compat_len);
  438. if (compatible && fdt_compat_len) {
  439. char *name;
  440. debug("Compatible: %s\n", compatible);
  441. name = strchr(compatible, ',');
  442. if (!name)
  443. return -EINVAL;
  444. name++;
  445. fdtfile = calloc(1, strlen(vendor) + strlen(name) +
  446. strlen(suffix) + 1);
  447. if (!fdtfile)
  448. return -ENOMEM;
  449. sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
  450. env_set("fdtfile", fdtfile);
  451. free(fdtfile);
  452. }
  453. return 0;
  454. }
  455. static u8 zynqmp_get_bootmode(void)
  456. {
  457. u8 bootmode;
  458. u32 reg = 0;
  459. int ret;
  460. ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
  461. if (ret)
  462. return -EINVAL;
  463. if (reg >> BOOT_MODE_ALT_SHIFT)
  464. reg >>= BOOT_MODE_ALT_SHIFT;
  465. bootmode = reg & BOOT_MODES_MASK;
  466. return bootmode;
  467. }
  468. int board_late_init(void)
  469. {
  470. u8 bootmode;
  471. struct udevice *dev;
  472. int bootseq = -1;
  473. int bootseq_len = 0;
  474. int env_targets_len = 0;
  475. const char *mode;
  476. char *new_targets;
  477. char *env_targets;
  478. int ret;
  479. #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
  480. usb_ether_init();
  481. #endif
  482. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  483. debug("Saved variables - Skipping\n");
  484. return 0;
  485. }
  486. if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
  487. return 0;
  488. ret = set_fdtfile();
  489. if (ret)
  490. return ret;
  491. bootmode = zynqmp_get_bootmode();
  492. puts("Bootmode: ");
  493. switch (bootmode) {
  494. case USB_MODE:
  495. puts("USB_MODE\n");
  496. mode = "usb";
  497. env_set("modeboot", "usb_dfu_spl");
  498. break;
  499. case JTAG_MODE:
  500. puts("JTAG_MODE\n");
  501. mode = "jtag pxe dhcp";
  502. env_set("modeboot", "jtagboot");
  503. break;
  504. case QSPI_MODE_24BIT:
  505. case QSPI_MODE_32BIT:
  506. mode = "qspi0";
  507. puts("QSPI_MODE\n");
  508. env_set("modeboot", "qspiboot");
  509. break;
  510. case EMMC_MODE:
  511. puts("EMMC_MODE\n");
  512. if (uclass_get_device_by_name(UCLASS_MMC,
  513. "mmc@ff160000", &dev) &&
  514. uclass_get_device_by_name(UCLASS_MMC,
  515. "sdhci@ff160000", &dev)) {
  516. puts("Boot from EMMC but without SD0 enabled!\n");
  517. return -1;
  518. }
  519. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  520. mode = "mmc";
  521. bootseq = dev->seq;
  522. break;
  523. case SD_MODE:
  524. puts("SD_MODE\n");
  525. if (uclass_get_device_by_name(UCLASS_MMC,
  526. "mmc@ff160000", &dev) &&
  527. uclass_get_device_by_name(UCLASS_MMC,
  528. "sdhci@ff160000", &dev)) {
  529. puts("Boot from SD0 but without SD0 enabled!\n");
  530. return -1;
  531. }
  532. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  533. mode = "mmc";
  534. bootseq = dev->seq;
  535. env_set("modeboot", "sdboot");
  536. break;
  537. case SD1_LSHFT_MODE:
  538. puts("LVL_SHFT_");
  539. /* fall through */
  540. case SD_MODE1:
  541. puts("SD_MODE1\n");
  542. if (uclass_get_device_by_name(UCLASS_MMC,
  543. "mmc@ff170000", &dev) &&
  544. uclass_get_device_by_name(UCLASS_MMC,
  545. "sdhci@ff170000", &dev)) {
  546. puts("Boot from SD1 but without SD1 enabled!\n");
  547. return -1;
  548. }
  549. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  550. mode = "mmc";
  551. bootseq = dev->seq;
  552. env_set("modeboot", "sdboot");
  553. break;
  554. case NAND_MODE:
  555. puts("NAND_MODE\n");
  556. mode = "nand0";
  557. env_set("modeboot", "nandboot");
  558. break;
  559. default:
  560. mode = "";
  561. printf("Invalid Boot Mode:0x%x\n", bootmode);
  562. break;
  563. }
  564. if (bootseq >= 0) {
  565. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  566. debug("Bootseq len: %x\n", bootseq_len);
  567. }
  568. /*
  569. * One terminating char + one byte for space between mode
  570. * and default boot_targets
  571. */
  572. env_targets = env_get("boot_targets");
  573. if (env_targets)
  574. env_targets_len = strlen(env_targets);
  575. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  576. bootseq_len);
  577. if (!new_targets)
  578. return -ENOMEM;
  579. if (bootseq >= 0)
  580. sprintf(new_targets, "%s%x %s", mode, bootseq,
  581. env_targets ? env_targets : "");
  582. else
  583. sprintf(new_targets, "%s %s", mode,
  584. env_targets ? env_targets : "");
  585. env_set("boot_targets", new_targets);
  586. reset_reason();
  587. return board_late_init_xilinx();
  588. }
  589. #endif
  590. int checkboard(void)
  591. {
  592. puts("Board: Xilinx ZynqMP\n");
  593. return 0;
  594. }