armada-xp-crs305-1g-4s.dtsi 2.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for CRS305-1G-4S board
  4. *
  5. * Copyright (C) 2016 Allied Telesis Labs
  6. * Copyright (C) 2020 Sartura Ltd.
  7. *
  8. * Based on armada-xp-db.dts
  9. *
  10. * Note: this Device Tree assumes that the bootloader has remapped the
  11. * internal registers to 0xf1000000 (instead of the default
  12. * 0xd0000000). The 0xf1000000 is the default used by the recent,
  13. * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  14. * boards were delivered with an older version of the bootloader that
  15. * left internal registers mapped at 0xd0000000. If you are in this
  16. * situation, you should either update your bootloader (preferred
  17. * solution) or the below Device Tree should be adjusted.
  18. */
  19. /dts-v1/;
  20. #include "armada-xp-98dx3236.dtsi"
  21. #include "armada-xp-crs305-1g-4s-u-boot.dtsi"
  22. / {
  23. model = "CRS305-1G-4S+";
  24. compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
  25. chosen {
  26. stdout-path = "serial0:115200n8";
  27. bootargs = "console=ttyS0,115200 earlyprintk";
  28. };
  29. aliases {
  30. spi0 = &spi0;
  31. };
  32. memory {
  33. device_type = "memory";
  34. reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
  35. };
  36. };
  37. &L2 {
  38. arm,parity-enable;
  39. marvell,ecc-enable;
  40. };
  41. &devbus_bootcs {
  42. status = "okay";
  43. /* Device Bus parameters are required */
  44. /* Read parameters */
  45. devbus,bus-width = <16>;
  46. devbus,turn-off-ps = <60000>;
  47. devbus,badr-skew-ps = <0>;
  48. devbus,acc-first-ps = <124000>;
  49. devbus,acc-next-ps = <248000>;
  50. devbus,rd-setup-ps = <0>;
  51. devbus,rd-hold-ps = <0>;
  52. /* Write parameters */
  53. devbus,sync-enable = <0>;
  54. devbus,wr-high-ps = <60000>;
  55. devbus,wr-low-ps = <60000>;
  56. devbus,ale-wr-ps = <60000>;
  57. };
  58. &uart0 {
  59. status = "okay";
  60. };
  61. &uart1 {
  62. status = "okay";
  63. };
  64. &i2c0 {
  65. clock-frequency = <100000>;
  66. status = "okay";
  67. };
  68. &usb0 {
  69. status = "okay";
  70. };
  71. &spi0 {
  72. status = "okay";
  73. spi-flash@0 {
  74. #address-cells = <1>;
  75. #size-cells = <1>;
  76. compatible = "spi-flash", "jedec,spi-nor";
  77. reg = <0>; /* Chip select 0 */
  78. spi-max-frequency = <108000000>;
  79. m25p,fast-read;
  80. partition@u-boot {
  81. reg = <0x00000000 0x00080000>;
  82. label = "u-boot";
  83. };
  84. partition@u-boot-env {
  85. reg = <0x00080000 0x00010000>;
  86. label = "u-boot-env";
  87. };
  88. partition@firmware {
  89. reg = <0x00090000 0x00f70000>;
  90. label = "firmware";
  91. };
  92. };
  93. };