sor.c 27 KB

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  1. /*
  2. * Copyright (c) 2011-2013, NVIDIA Corporation.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch-tegra/dc.h>
  13. #include "displayport.h"
  14. #include "sor.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define DEBUG_SOR 0
  17. #define APBDEV_PMC_DPD_SAMPLE 0x20
  18. #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE 0
  19. #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE 1
  20. #define APBDEV_PMC_SEL_DPD_TIM 0x1c8
  21. #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT 0x7f
  22. #define APBDEV_PMC_IO_DPD2_REQ 0x1c0
  23. #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT 25
  24. #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25)
  25. #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
  26. #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT 30
  27. #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30)
  28. #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30)
  29. #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
  30. #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
  31. #define APBDEV_PMC_IO_DPD2_STATUS 0x1c4
  32. #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT 25
  33. #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
  34. #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
  35. static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
  36. {
  37. return readl((u32 *)sor->base + reg);
  38. }
  39. static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
  40. u32 val)
  41. {
  42. writel(val, (u32 *)sor->base + reg);
  43. }
  44. static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
  45. u32 reg, u32 mask, u32 val)
  46. {
  47. u32 reg_val = tegra_sor_readl(sor, reg);
  48. reg_val &= ~mask;
  49. reg_val |= val;
  50. tegra_sor_writel(sor, reg, reg_val);
  51. }
  52. void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor)
  53. {
  54. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  55. DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE);
  56. }
  57. void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, u32 pe_reg,
  58. u32 vs_reg, u32 pc_reg, u8 pc_supported)
  59. {
  60. tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);
  61. tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);
  62. if (pc_supported) {
  63. tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask,
  64. pc_reg);
  65. }
  66. }
  67. static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
  68. u32 mask, u32 exp_val,
  69. int poll_interval_us, int timeout_ms)
  70. {
  71. u32 reg_val = 0;
  72. ulong start;
  73. start = get_timer(0);
  74. do {
  75. reg_val = tegra_sor_readl(sor, reg);
  76. if (((reg_val & mask) == exp_val))
  77. return 0;
  78. udelay(poll_interval_us);
  79. } while (get_timer(start) < timeout_ms);
  80. debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
  81. reg, reg_val, mask, exp_val);
  82. return -ETIMEDOUT;
  83. }
  84. int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
  85. {
  86. u32 reg_val;
  87. u32 orig_val;
  88. orig_val = tegra_sor_readl(sor, PWR);
  89. reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
  90. PWR_NORMAL_STATE_PD; /* normal state only */
  91. if (reg_val == orig_val)
  92. return 0; /* No update needed */
  93. reg_val |= PWR_SETTING_NEW_TRIGGER;
  94. tegra_sor_writel(sor, PWR, reg_val);
  95. /* Poll to confirm it is done */
  96. if (tegra_dc_sor_poll_register(sor, PWR,
  97. PWR_SETTING_NEW_DEFAULT_MASK,
  98. PWR_SETTING_NEW_DONE,
  99. 100, TEGRA_SOR_TIMEOUT_MS)) {
  100. debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
  101. return -EFAULT;
  102. }
  103. return 0;
  104. }
  105. void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
  106. u8 training_pattern,
  107. const struct tegra_dp_link_config *link_cfg)
  108. {
  109. u32 reg_val;
  110. reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
  111. if (ena)
  112. reg_val |= DP_LINKCTL_ENABLE_YES;
  113. else
  114. reg_val &= DP_LINKCTL_ENABLE_NO;
  115. reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
  116. reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
  117. if (link_cfg->enhanced_framing)
  118. reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
  119. tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
  120. switch (training_pattern) {
  121. case training_pattern_1:
  122. tegra_sor_writel(sor, DP_TPG, 0x41414141);
  123. break;
  124. case training_pattern_2:
  125. case training_pattern_3:
  126. reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
  127. 0x43434343 : 0x42424242;
  128. tegra_sor_writel(sor, DP_TPG, reg_val);
  129. break;
  130. default:
  131. tegra_sor_writel(sor, DP_TPG, 0x50505050);
  132. break;
  133. }
  134. }
  135. static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
  136. int pu, int is_lvds)
  137. {
  138. u32 reg_val;
  139. /* SOR lane sequencer */
  140. if (pu) {
  141. reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
  142. LANE_SEQ_CTL_SEQUENCE_DOWN |
  143. LANE_SEQ_CTL_NEW_POWER_STATE_PU;
  144. } else {
  145. reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
  146. LANE_SEQ_CTL_SEQUENCE_UP |
  147. LANE_SEQ_CTL_NEW_POWER_STATE_PD;
  148. }
  149. if (is_lvds)
  150. reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
  151. else
  152. reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
  153. tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
  154. if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
  155. LANE_SEQ_CTL_SETTING_MASK,
  156. LANE_SEQ_CTL_SETTING_NEW_DONE,
  157. 100, TEGRA_SOR_TIMEOUT_MS)) {
  158. debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
  159. return -1;
  160. }
  161. return 0;
  162. }
  163. static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
  164. u32 lane_count, int pu)
  165. {
  166. u32 reg_val;
  167. reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
  168. if (pu) {
  169. switch (lane_count) {
  170. case 4:
  171. reg_val |= (DP_PADCTL_PD_TXD_3_NO |
  172. DP_PADCTL_PD_TXD_2_NO);
  173. /* fall through */
  174. case 2:
  175. reg_val |= DP_PADCTL_PD_TXD_1_NO;
  176. case 1:
  177. reg_val |= DP_PADCTL_PD_TXD_0_NO;
  178. break;
  179. default:
  180. debug("dp: invalid lane number %d\n", lane_count);
  181. return -1;
  182. }
  183. tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
  184. tegra_dc_sor_set_lane_count(sor, lane_count);
  185. }
  186. return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
  187. }
  188. void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
  189. int power_up)
  190. {
  191. u32 reg_val;
  192. reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
  193. if (power_up)
  194. reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
  195. else
  196. reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
  197. tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
  198. }
  199. static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
  200. u32 pwm_dutycycle)
  201. {
  202. tegra_sor_writel(sor, PWM_DIV, pwm_div);
  203. tegra_sor_writel(sor, PWM_CTL,
  204. (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
  205. PWM_CTL_SETTING_NEW_TRIGGER);
  206. if (tegra_dc_sor_poll_register(sor, PWM_CTL,
  207. PWM_CTL_SETTING_NEW_SHIFT,
  208. PWM_CTL_SETTING_NEW_DONE,
  209. 100, TEGRA_SOR_TIMEOUT_MS)) {
  210. debug("dp: timeout while waiting for SOR PWM setting\n");
  211. }
  212. }
  213. static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
  214. const struct tegra_dp_link_config *link_cfg)
  215. {
  216. u32 reg_val;
  217. tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
  218. tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
  219. reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
  220. reg_val &= ~DP_CONFIG_WATERMARK_MASK;
  221. reg_val |= link_cfg->watermark;
  222. reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
  223. reg_val |= (link_cfg->active_count <<
  224. DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
  225. reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
  226. reg_val |= (link_cfg->active_frac <<
  227. DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
  228. if (link_cfg->activepolarity)
  229. reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
  230. else
  231. reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
  232. reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
  233. DP_CONFIG_RD_RESET_VAL_NEGATIVE);
  234. tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
  235. /* program h/vblank sym */
  236. tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
  237. DP_AUDIO_HBLANK_SYMBOLS_MASK,
  238. link_cfg->hblank_sym);
  239. tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
  240. DP_AUDIO_VBLANK_SYMBOLS_MASK,
  241. link_cfg->vblank_sym);
  242. }
  243. static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
  244. {
  245. tegra_sor_writel(sor, SUPER_STATE0, 0);
  246. tegra_sor_writel(sor, SUPER_STATE0, 1);
  247. tegra_sor_writel(sor, SUPER_STATE0, 0);
  248. }
  249. static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
  250. {
  251. tegra_sor_writel(sor, STATE0, 0);
  252. tegra_sor_writel(sor, STATE0, 1);
  253. tegra_sor_writel(sor, STATE0, 0);
  254. }
  255. static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
  256. {
  257. u32 reg_val;
  258. void *pmc_base = sor->pmc_base;
  259. if (up) {
  260. writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
  261. pmc_base + APBDEV_PMC_DPD_SAMPLE);
  262. writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
  263. }
  264. reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
  265. reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
  266. APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
  267. reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
  268. APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
  269. APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
  270. APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
  271. writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
  272. /* Polling */
  273. u32 temp = 10 * 1000;
  274. do {
  275. udelay(20);
  276. reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
  277. if (temp > 20)
  278. temp -= 20;
  279. else
  280. break;
  281. } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
  282. if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
  283. debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
  284. return -EIO;
  285. }
  286. if (up) {
  287. writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
  288. pmc_base + APBDEV_PMC_DPD_SAMPLE);
  289. }
  290. return 0;
  291. }
  292. void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
  293. {
  294. u32 reg_val;
  295. reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
  296. if (is_int)
  297. reg_val |= DP_SPARE_PANEL_INTERNAL;
  298. else
  299. reg_val &= ~DP_SPARE_PANEL_INTERNAL;
  300. reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
  301. DP_SPARE_SEQ_ENABLE_YES;
  302. tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
  303. }
  304. void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
  305. u8 *lane_count)
  306. {
  307. u32 reg_val;
  308. reg_val = tegra_sor_readl(sor, CLK_CNTRL);
  309. *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
  310. >> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
  311. reg_val = tegra_sor_readl(sor,
  312. DP_LINKCTL(sor->portnum));
  313. switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
  314. case DP_LINKCTL_LANECOUNT_ZERO:
  315. *lane_count = 0;
  316. break;
  317. case DP_LINKCTL_LANECOUNT_ONE:
  318. *lane_count = 1;
  319. break;
  320. case DP_LINKCTL_LANECOUNT_TWO:
  321. *lane_count = 2;
  322. break;
  323. case DP_LINKCTL_LANECOUNT_FOUR:
  324. *lane_count = 4;
  325. break;
  326. default:
  327. printf("Unknown lane count\n");
  328. }
  329. }
  330. void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
  331. {
  332. tegra_sor_write_field(sor, CLK_CNTRL,
  333. CLK_CNTRL_DP_LINK_SPEED_MASK,
  334. link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
  335. }
  336. void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
  337. {
  338. u32 reg_val;
  339. reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
  340. reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
  341. switch (lane_count) {
  342. case 0:
  343. break;
  344. case 1:
  345. reg_val |= DP_LINKCTL_LANECOUNT_ONE;
  346. break;
  347. case 2:
  348. reg_val |= DP_LINKCTL_LANECOUNT_TWO;
  349. break;
  350. case 4:
  351. reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
  352. break;
  353. default:
  354. /* 0 should be handled earlier. */
  355. printf("dp: Invalid lane count %d\n", lane_count);
  356. return;
  357. }
  358. tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
  359. }
  360. /*
  361. * The SOR power sequencer does not work for t124 so SW has to
  362. * go through the power sequence manually
  363. * Power up steps from spec:
  364. * STEP PDPORT PDPLL PDBG PLLVCOD PLLCAPD E_DPD PDCAL
  365. * 1 1 1 1 1 1 1 1
  366. * 2 1 1 1 1 1 0 1
  367. * 3 1 1 0 1 1 0 1
  368. * 4 1 0 0 0 0 0 1
  369. * 5 0 0 0 0 0 0 1
  370. */
  371. static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds)
  372. {
  373. int ret;
  374. if (sor->power_is_up)
  375. return 0;
  376. /* Set link bw */
  377. tegra_dc_sor_set_link_bandwidth(sor, is_lvds ?
  378. CLK_CNTRL_DP_LINK_SPEED_LVDS :
  379. CLK_CNTRL_DP_LINK_SPEED_G1_62);
  380. /* step 1 */
  381. tegra_sor_write_field(sor, PLL2,
  382. PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
  383. PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
  384. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
  385. PLL2_AUX7_PORT_POWERDOWN_ENABLE |
  386. PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
  387. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
  388. tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
  389. PLL0_VCOPD_MASK, /* PLLVCOPD */
  390. PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
  391. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  392. DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
  393. DP_PADCTL_PAD_CAL_PD_POWERDOWN);
  394. /* step 2 */
  395. ret = tegra_dc_sor_io_set_dpd(sor, 1);
  396. if (ret)
  397. return ret;
  398. udelay(15);
  399. /* step 3 */
  400. tegra_sor_write_field(sor, PLL2,
  401. PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
  402. PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
  403. udelay(25);
  404. /* step 4 */
  405. tegra_sor_write_field(sor, PLL0,
  406. PLL0_PWR_MASK | /* PDPLL */
  407. PLL0_VCOPD_MASK, /* PLLVCOPD */
  408. PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
  409. /* PLLCAPD */
  410. tegra_sor_write_field(sor, PLL2,
  411. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
  412. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
  413. udelay(225);
  414. /* step 5 PDPORT */
  415. tegra_sor_write_field(sor, PLL2,
  416. PLL2_AUX7_PORT_POWERDOWN_MASK,
  417. PLL2_AUX7_PORT_POWERDOWN_DISABLE);
  418. sor->power_is_up = 1;
  419. return 0;
  420. }
  421. #if DEBUG_SOR
  422. static void dump_sor_reg(struct tegra_dc_sor_data *sor)
  423. {
  424. #define DUMP_REG(a) printk(BIOS_INFO, "%-32s %03x %08x\n", \
  425. #a, a, tegra_sor_readl(sor, a));
  426. DUMP_REG(SUPER_STATE0);
  427. DUMP_REG(SUPER_STATE1);
  428. DUMP_REG(STATE0);
  429. DUMP_REG(STATE1);
  430. DUMP_REG(NV_HEAD_STATE0(0));
  431. DUMP_REG(NV_HEAD_STATE0(1));
  432. DUMP_REG(NV_HEAD_STATE1(0));
  433. DUMP_REG(NV_HEAD_STATE1(1));
  434. DUMP_REG(NV_HEAD_STATE2(0));
  435. DUMP_REG(NV_HEAD_STATE2(1));
  436. DUMP_REG(NV_HEAD_STATE3(0));
  437. DUMP_REG(NV_HEAD_STATE3(1));
  438. DUMP_REG(NV_HEAD_STATE4(0));
  439. DUMP_REG(NV_HEAD_STATE4(1));
  440. DUMP_REG(NV_HEAD_STATE5(0));
  441. DUMP_REG(NV_HEAD_STATE5(1));
  442. DUMP_REG(CRC_CNTRL);
  443. DUMP_REG(CLK_CNTRL);
  444. DUMP_REG(CAP);
  445. DUMP_REG(PWR);
  446. DUMP_REG(TEST);
  447. DUMP_REG(PLL0);
  448. DUMP_REG(PLL1);
  449. DUMP_REG(PLL2);
  450. DUMP_REG(PLL3);
  451. DUMP_REG(CSTM);
  452. DUMP_REG(LVDS);
  453. DUMP_REG(CRCA);
  454. DUMP_REG(CRCB);
  455. DUMP_REG(SEQ_CTL);
  456. DUMP_REG(LANE_SEQ_CTL);
  457. DUMP_REG(SEQ_INST(0));
  458. DUMP_REG(SEQ_INST(1));
  459. DUMP_REG(SEQ_INST(2));
  460. DUMP_REG(SEQ_INST(3));
  461. DUMP_REG(SEQ_INST(4));
  462. DUMP_REG(SEQ_INST(5));
  463. DUMP_REG(SEQ_INST(6));
  464. DUMP_REG(SEQ_INST(7));
  465. DUMP_REG(SEQ_INST(8));
  466. DUMP_REG(PWM_DIV);
  467. DUMP_REG(PWM_CTL);
  468. DUMP_REG(MSCHECK);
  469. DUMP_REG(XBAR_CTRL);
  470. DUMP_REG(DP_LINKCTL(0));
  471. DUMP_REG(DP_LINKCTL(1));
  472. DUMP_REG(DC(0));
  473. DUMP_REG(DC(1));
  474. DUMP_REG(LANE_DRIVE_CURRENT(0));
  475. DUMP_REG(PR(0));
  476. DUMP_REG(LANE4_PREEMPHASIS(0));
  477. DUMP_REG(POSTCURSOR(0));
  478. DUMP_REG(DP_CONFIG(0));
  479. DUMP_REG(DP_CONFIG(1));
  480. DUMP_REG(DP_MN(0));
  481. DUMP_REG(DP_MN(1));
  482. DUMP_REG(DP_PADCTL(0));
  483. DUMP_REG(DP_PADCTL(1));
  484. DUMP_REG(DP_DEBUG(0));
  485. DUMP_REG(DP_DEBUG(1));
  486. DUMP_REG(DP_SPARE(0));
  487. DUMP_REG(DP_SPARE(1));
  488. DUMP_REG(DP_TPG);
  489. return;
  490. }
  491. #endif
  492. static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
  493. int is_lvds,
  494. const struct tegra_dp_link_config *link_cfg,
  495. const struct display_timing *timing)
  496. {
  497. const int head_num = 0;
  498. u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num;
  499. u32 vtotal, htotal;
  500. u32 vsync_end, hsync_end;
  501. u32 vblank_end, hblank_end;
  502. u32 vblank_start, hblank_start;
  503. reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
  504. STATE1_ASY_PROTOCOL_DP_A;
  505. reg_val |= STATE1_ASY_SUBOWNER_NONE |
  506. STATE1_ASY_CRCMODE_COMPLETE_RASTER;
  507. reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
  508. reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
  509. reg_val |= (link_cfg->bits_per_pixel > 18) ?
  510. STATE1_ASY_PIXELDEPTH_BPP_24_444 :
  511. STATE1_ASY_PIXELDEPTH_BPP_18_444;
  512. tegra_sor_writel(sor, STATE1, reg_val);
  513. /*
  514. * Skipping programming NV_HEAD_STATE0, assuming:
  515. * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
  516. */
  517. vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
  518. timing->vactive.typ + timing->vfront_porch.typ;
  519. htotal = timing->hsync_len.typ + timing->hback_porch.typ +
  520. timing->hactive.typ + timing->hfront_porch.typ;
  521. tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
  522. vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
  523. htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
  524. vsync_end = timing->vsync_len.typ - 1;
  525. hsync_end = timing->hsync_len.typ - 1;
  526. tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
  527. vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
  528. hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
  529. vblank_end = vsync_end + timing->vback_porch.typ;
  530. hblank_end = hsync_end + timing->hback_porch.typ;
  531. tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
  532. vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
  533. hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
  534. vblank_start = vblank_end + timing->vactive.typ;
  535. hblank_start = hblank_end + timing->hactive.typ;
  536. tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
  537. vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
  538. hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
  539. /* TODO: adding interlace mode support */
  540. tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
  541. tegra_sor_write_field(sor, CSTM,
  542. CSTM_ROTCLK_DEFAULT_MASK |
  543. CSTM_LVDS_EN_ENABLE,
  544. 2 << CSTM_ROTCLK_SHIFT |
  545. is_lvds ? CSTM_LVDS_EN_ENABLE :
  546. CSTM_LVDS_EN_DISABLE);
  547. tegra_dc_sor_config_pwm(sor, 1024, 1024);
  548. }
  549. static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
  550. {
  551. u32 reg_val = readl(&disp_ctrl->cmd.state_access);
  552. writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  553. writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
  554. /* Enable DC now - otherwise pure text console may not show. */
  555. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  556. &disp_ctrl->cmd.disp_cmd);
  557. writel(reg_val, &disp_ctrl->cmd.state_access);
  558. }
  559. int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
  560. const struct tegra_dp_link_config *link_cfg)
  561. {
  562. int ret;
  563. tegra_sor_write_field(sor, CLK_CNTRL,
  564. CLK_CNTRL_DP_CLK_SEL_MASK,
  565. CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
  566. tegra_sor_write_field(sor, PLL2,
  567. PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
  568. PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
  569. udelay(25);
  570. tegra_sor_write_field(sor, PLL3,
  571. PLL3_PLLVDD_MODE_MASK,
  572. PLL3_PLLVDD_MODE_V3_3);
  573. tegra_sor_writel(sor, PLL0,
  574. 0xf << PLL0_ICHPMP_SHFIT |
  575. 0x3 << PLL0_VCOCAP_SHIFT |
  576. PLL0_PLLREG_LEVEL_V45 |
  577. PLL0_RESISTORSEL_EXT |
  578. PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
  579. tegra_sor_write_field(sor, PLL2,
  580. PLL2_AUX1_SEQ_MASK |
  581. PLL2_AUX9_LVDSEN_OVERRIDE |
  582. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
  583. PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
  584. PLL2_AUX9_LVDSEN_OVERRIDE |
  585. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
  586. tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
  587. PLL1_TMDS_TERM_ENABLE);
  588. if (tegra_dc_sor_poll_register(sor, PLL2,
  589. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
  590. PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
  591. 100, TEGRA_SOR_TIMEOUT_MS)) {
  592. printf("DP failed to lock PLL\n");
  593. return -EIO;
  594. }
  595. tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
  596. PLL2_AUX7_PORT_POWERDOWN_MASK,
  597. PLL2_AUX2_OVERRIDE_POWERDOWN |
  598. PLL2_AUX7_PORT_POWERDOWN_DISABLE);
  599. ret = tegra_dc_sor_power_up(sor, 0);
  600. if (ret) {
  601. debug("DP failed to power up\n");
  602. return ret;
  603. }
  604. /* re-enable SOR clock */
  605. clock_sor_enable_edp_clock();
  606. /* Power up lanes */
  607. tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
  608. tegra_dc_sor_set_dp_mode(sor, link_cfg);
  609. debug("%s ret\n", __func__);
  610. return 0;
  611. }
  612. int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
  613. const struct tegra_dp_link_config *link_cfg,
  614. const struct display_timing *timing)
  615. {
  616. const void *blob = gd->fdt_blob;
  617. struct dc_ctlr *disp_ctrl;
  618. u32 reg_val;
  619. int node;
  620. /* Use the first display controller */
  621. debug("%s\n", __func__);
  622. node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
  623. if (node < 0)
  624. return -ENOENT;
  625. disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
  626. tegra_dc_sor_enable_dc(disp_ctrl);
  627. tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
  628. writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
  629. writel(0x9f, &disp_ctrl->cmd.state_ctrl);
  630. writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
  631. PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
  632. &disp_ctrl->cmd.disp_pow_ctrl);
  633. reg_val = tegra_sor_readl(sor, TEST);
  634. if (reg_val & TEST_ATTACHED_TRUE)
  635. return -EEXIST;
  636. tegra_sor_writel(sor, SUPER_STATE1,
  637. SUPER_STATE1_ATTACHED_NO);
  638. /*
  639. * Enable display2sor clock at least 2 cycles before DC start,
  640. * to clear sor internal valid signal.
  641. */
  642. writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
  643. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  644. writel(0, &disp_ctrl->disp.disp_win_opt);
  645. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  646. /* Attach head */
  647. tegra_dc_sor_update(sor);
  648. tegra_sor_writel(sor, SUPER_STATE1,
  649. SUPER_STATE1_ATTACHED_YES);
  650. tegra_sor_writel(sor, SUPER_STATE1,
  651. SUPER_STATE1_ATTACHED_YES |
  652. SUPER_STATE1_ASY_HEAD_OP_AWAKE |
  653. SUPER_STATE1_ASY_ORMODE_NORMAL);
  654. tegra_dc_sor_super_update(sor);
  655. /* Enable dc */
  656. reg_val = readl(&disp_ctrl->cmd.state_access);
  657. writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  658. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  659. &disp_ctrl->cmd.disp_cmd);
  660. writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
  661. writel(reg_val, &disp_ctrl->cmd.state_access);
  662. if (tegra_dc_sor_poll_register(sor, TEST,
  663. TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
  664. TEST_ACT_HEAD_OPMODE_AWAKE,
  665. 100,
  666. TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
  667. printf("dc timeout waiting for OPMOD = AWAKE\n");
  668. return -ETIMEDOUT;
  669. } else {
  670. debug("%s: sor is attached\n", __func__);
  671. }
  672. #if DEBUG_SOR
  673. dump_sor_reg(sor);
  674. #endif
  675. debug("%s: ret=%d\n", __func__, 0);
  676. return 0;
  677. }
  678. void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
  679. const struct tegra_dp_link_config *link_cfg)
  680. {
  681. tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
  682. link_cfg->drive_current);
  683. tegra_sor_writel(sor, PR(sor->portnum),
  684. link_cfg->preemphasis);
  685. tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
  686. link_cfg->postcursor);
  687. tegra_sor_writel(sor, LVDS, 0);
  688. tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
  689. tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
  690. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  691. DP_PADCTL_TX_PU_ENABLE |
  692. DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
  693. DP_PADCTL_TX_PU_ENABLE |
  694. 2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
  695. /* Precharge */
  696. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
  697. udelay(20);
  698. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
  699. }
  700. int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor,
  701. const struct tegra_dp_link_config *link_cfg)
  702. {
  703. u32 drive_current = 0;
  704. u32 pre_emphasis = 0;
  705. /* Set to a known-good pre-calibrated setting */
  706. switch (link_cfg->link_bw) {
  707. case SOR_LINK_SPEED_G1_62:
  708. case SOR_LINK_SPEED_G2_7:
  709. drive_current = 0x13131313;
  710. pre_emphasis = 0;
  711. break;
  712. case SOR_LINK_SPEED_G5_4:
  713. debug("T124 does not support 5.4G link clock.\n");
  714. default:
  715. debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
  716. return -ENOLINK;
  717. }
  718. tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current);
  719. tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
  720. return 0;
  721. }
  722. void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
  723. const struct tegra_dp_link_config *link_cfg)
  724. {
  725. u32 pad_ctrl = 0;
  726. int err = 0;
  727. switch (link_cfg->lane_count) {
  728. case 4:
  729. pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
  730. DP_PADCTL_PD_TXD_1_NO |
  731. DP_PADCTL_PD_TXD_2_NO |
  732. DP_PADCTL_PD_TXD_3_NO;
  733. break;
  734. case 2:
  735. pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
  736. DP_PADCTL_PD_TXD_1_NO |
  737. DP_PADCTL_PD_TXD_2_YES |
  738. DP_PADCTL_PD_TXD_3_YES;
  739. break;
  740. case 1:
  741. pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
  742. DP_PADCTL_PD_TXD_1_YES |
  743. DP_PADCTL_PD_TXD_2_YES |
  744. DP_PADCTL_PD_TXD_3_YES;
  745. break;
  746. default:
  747. printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
  748. return;
  749. }
  750. pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
  751. tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
  752. err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
  753. if (err) {
  754. debug("Wait for lane power down failed: %d\n", err);
  755. return;
  756. }
  757. }
  758. int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor,
  759. const struct tegra_dp_link_config *cfg)
  760. {
  761. u32 val = 0;
  762. switch (cfg->lane_count) {
  763. case 4:
  764. val |= (DP_PADCTL_PD_TXD_3_NO |
  765. DP_PADCTL_PD_TXD_2_NO);
  766. /* fall through */
  767. case 2:
  768. val |= DP_PADCTL_PD_TXD_1_NO;
  769. /* fall through */
  770. case 1:
  771. val |= DP_PADCTL_PD_TXD_0_NO;
  772. break;
  773. default:
  774. debug("dp: invalid lane number %d\n", cfg->lane_count);
  775. return -EINVAL;
  776. }
  777. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  778. (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
  779. (val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
  780. udelay(100);
  781. tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  782. (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
  783. 0);
  784. return 0;
  785. }
  786. static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable)
  787. {
  788. u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);
  789. reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE;
  790. writel(reg_val, &disp_ctrl->disp.disp_win_opt);
  791. }
  792. int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
  793. {
  794. int dc_reg_ctx[DC_REG_SAVE_SPACE];
  795. const void *blob = gd->fdt_blob;
  796. struct dc_ctlr *disp_ctrl;
  797. unsigned long dc_int_mask;
  798. int node;
  799. int ret;
  800. debug("%s\n", __func__);
  801. /* Use the first display controller */
  802. node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
  803. if (node < 0) {
  804. ret = -ENOENT;
  805. goto err;
  806. }
  807. disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
  808. /* Sleep mode */
  809. tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
  810. SUPER_STATE1_ASY_ORMODE_SAFE |
  811. SUPER_STATE1_ATTACHED_YES);
  812. tegra_dc_sor_super_update(sor);
  813. tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);
  814. if (tegra_dc_sor_poll_register(sor, TEST,
  815. TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
  816. TEST_ACT_HEAD_OPMODE_SLEEP, 100,
  817. TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
  818. debug("dc timeout waiting for OPMOD = SLEEP\n");
  819. ret = -ETIMEDOUT;
  820. goto err;
  821. }
  822. tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
  823. SUPER_STATE1_ASY_ORMODE_SAFE |
  824. SUPER_STATE1_ATTACHED_NO);
  825. /* Mask DC interrupts during the 2 dummy frames required for detach */
  826. dc_int_mask = readl(&disp_ctrl->cmd.int_mask);
  827. writel(0, &disp_ctrl->cmd.int_mask);
  828. /* Stop DC->SOR path */
  829. tegra_dc_sor_enable_sor(disp_ctrl, false);
  830. ret = tegra_dc_sor_general_act(disp_ctrl);
  831. if (ret)
  832. goto err;
  833. /* Stop DC */
  834. writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);
  835. ret = tegra_dc_sor_general_act(disp_ctrl);
  836. if (ret)
  837. goto err;
  838. tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);
  839. writel(dc_int_mask, &disp_ctrl->cmd.int_mask);
  840. return 0;
  841. err:
  842. debug("%s: ret=%d\n", __func__, ret);
  843. return ret;
  844. }
  845. int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp)
  846. {
  847. const void *blob = gd->fdt_blob;
  848. struct tegra_dc_sor_data *sor;
  849. int node;
  850. node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
  851. if (node < 0)
  852. return -ENOENT;
  853. sor = calloc(1, sizeof(*sor));
  854. if (!sor)
  855. return -ENOMEM;
  856. sor->base = (void *)fdtdec_get_addr(blob, node, "reg");
  857. node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
  858. if (node < 0)
  859. return -ENOENT;
  860. sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
  861. sor->power_is_up = 0;
  862. sor->portnum = 0;
  863. *sorp = sor;
  864. return 0;
  865. }