displayport.h 13 KB

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  1. /*
  2. * Copyright (c) 2014, NVIDIA Corporation.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef _TEGRA_DISPLAYPORT_H
  7. #define _TEGRA_DISPLAYPORT_H
  8. #include <linux/drm_dp_helper.h>
  9. struct dpaux_ctlr {
  10. u32 reserved0;
  11. u32 intr_en_aux;
  12. u32 reserved2_4;
  13. u32 intr_aux;
  14. };
  15. #define DPAUX_INTR_EN_AUX 0x1
  16. #define DPAUX_INTR_AUX 0x5
  17. #define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i))
  18. #define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i))
  19. #define DPAUX_DP_AUXADDR 0x29
  20. #define DPAUX_DP_AUXCTL 0x2d
  21. #define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0
  22. #define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff
  23. #define DPAUX_DP_AUXCTL_CMD_SHIFT 12
  24. #define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12)
  25. #define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12)
  26. #define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12)
  27. #define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12)
  28. #define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12)
  29. #define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12)
  30. #define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12)
  31. #define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12)
  32. #define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12)
  33. #define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16
  34. #define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16)
  35. #define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16)
  36. #define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16)
  37. #define DPAUX_DP_AUXCTL_RST_SHIFT 31
  38. #define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31)
  39. #define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31)
  40. #define DPAUX_DP_AUXSTAT 0x31
  41. #define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28
  42. #define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28)
  43. #define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28)
  44. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20
  45. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20)
  46. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20)
  47. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20)
  48. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20)
  49. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20)
  50. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20)
  51. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20)
  52. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20)
  53. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20)
  54. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20)
  55. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20)
  56. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20)
  57. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20)
  58. #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20)
  59. #define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16
  60. #define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16)
  61. #define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16)
  62. #define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16)
  63. #define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16)
  64. #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16)
  65. #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16)
  66. #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11
  67. #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11)
  68. #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11)
  69. #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10
  70. #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10)
  71. #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10)
  72. #define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9
  73. #define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9)
  74. #define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9)
  75. #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8
  76. #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8)
  77. #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8)
  78. #define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0
  79. #define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0)
  80. #define DPAUX_HPD_CONFIG (0x3d)
  81. #define DPAUX_HPD_IRQ_CONFIG 0x41
  82. #define DPAUX_DP_AUX_CONFIG 0x45
  83. #define DPAUX_HYBRID_PADCTL 0x49
  84. #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15
  85. #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15)
  86. #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15)
  87. #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14
  88. #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14)
  89. #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14)
  90. #define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12
  91. #define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12)
  92. #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12)
  93. #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12)
  94. #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12)
  95. #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12)
  96. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8
  97. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8)
  98. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8)
  99. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8)
  100. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8)
  101. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8)
  102. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8)
  103. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8)
  104. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8)
  105. #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8)
  106. #define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2
  107. #define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2)
  108. #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1
  109. #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1)
  110. #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1)
  111. #define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0
  112. #define DPAUX_HYBRID_PADCTL_MODE_AUX 0
  113. #define DPAUX_HYBRID_PADCTL_MODE_I2C 1
  114. #define DPAUX_HYBRID_SPARE 0x4d
  115. #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0
  116. #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1
  117. #define DP_AUX_DEFER_MAX_TRIES 7
  118. #define DP_AUX_TIMEOUT_MAX_TRIES 2
  119. #define DP_POWER_ON_MAX_TRIES 3
  120. #define DP_AUX_MAX_BYTES 16
  121. #define DP_AUX_TIMEOUT_MS 40
  122. #define DP_DPCP_RETRY_SLEEP_NS 400
  123. static const u32 tegra_dp_vs_regs[][4][4] = {
  124. /* postcursor2 L0 */
  125. {
  126. /* pre-emphasis: L0, L1, L2, L3 */
  127. {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */
  128. {0x1e, 0x25, 0x2d}, /* L1 */
  129. {0x28, 0x32}, /* L2 */
  130. {0x3c}, /* L3 */
  131. },
  132. /* postcursor2 L1 */
  133. {
  134. {0x12, 0x17, 0x1b, 0x25},
  135. {0x1c, 0x23, 0x2a},
  136. {0x25, 0x2f},
  137. {0x39},
  138. },
  139. /* postcursor2 L2 */
  140. {
  141. {0x12, 0x16, 0x1a, 0x22},
  142. {0x1b, 0x20, 0x27},
  143. {0x24, 0x2d},
  144. {0x36},
  145. },
  146. /* postcursor2 L3 */
  147. {
  148. {0x11, 0x14, 0x17, 0x1f},
  149. {0x19, 0x1e, 0x24},
  150. {0x22, 0x2a},
  151. {0x32},
  152. },
  153. };
  154. static const u32 tegra_dp_pe_regs[][4][4] = {
  155. /* postcursor2 L0 */
  156. {
  157. /* pre-emphasis: L0, L1, L2, L3 */
  158. {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */
  159. {0x00, 0x0f, 0x1e}, /* L1 */
  160. {0x00, 0x14}, /* L2 */
  161. {0x00}, /* L3 */
  162. },
  163. /* postcursor2 L1 */
  164. {
  165. {0x00, 0x0a, 0x14, 0x28},
  166. {0x00, 0x0f, 0x1e},
  167. {0x00, 0x14},
  168. {0x00},
  169. },
  170. /* postcursor2 L2 */
  171. {
  172. {0x00, 0x0a, 0x14, 0x28},
  173. {0x00, 0x0f, 0x1e},
  174. {0x00, 0x14},
  175. {0x00},
  176. },
  177. /* postcursor2 L3 */
  178. {
  179. {0x00, 0x0a, 0x14, 0x28},
  180. {0x00, 0x0f, 0x1e},
  181. {0x00, 0x14},
  182. {0x00},
  183. },
  184. };
  185. static const u32 tegra_dp_pc_regs[][4][4] = {
  186. /* postcursor2 L0 */
  187. {
  188. /* pre-emphasis: L0, L1, L2, L3 */
  189. {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */
  190. {0x00, 0x00, 0x00}, /* L1 */
  191. {0x00, 0x00}, /* L2 */
  192. {0x00}, /* L3 */
  193. },
  194. /* postcursor2 L1 */
  195. {
  196. {0x02, 0x02, 0x04, 0x05},
  197. {0x02, 0x04, 0x05},
  198. {0x04, 0x05},
  199. {0x05},
  200. },
  201. /* postcursor2 L2 */
  202. {
  203. {0x04, 0x05, 0x08, 0x0b},
  204. {0x05, 0x09, 0x0b},
  205. {0x08, 0x0a},
  206. {0x0b},
  207. },
  208. /* postcursor2 L3 */
  209. {
  210. {0x05, 0x09, 0x0b, 0x12},
  211. {0x09, 0x0d, 0x12},
  212. {0x0b, 0x0f},
  213. {0x12},
  214. },
  215. };
  216. static const u32 tegra_dp_tx_pu[][4][4] = {
  217. /* postcursor2 L0 */
  218. {
  219. /* pre-emphasis: L0, L1, L2, L3 */
  220. {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */
  221. {0x30, 0x40, 0x60}, /* L1 */
  222. {0x40, 0x60}, /* L2 */
  223. {0x60}, /* L3 */
  224. },
  225. /* postcursor2 L1 */
  226. {
  227. {0x20, 0x20, 0x30, 0x50},
  228. {0x30, 0x40, 0x50},
  229. {0x40, 0x50},
  230. {0x60},
  231. },
  232. /* postcursor2 L2 */
  233. {
  234. {0x20, 0x20, 0x30, 0x40},
  235. {0x30, 0x30, 0x40},
  236. {0x40, 0x50},
  237. {0x60},
  238. },
  239. /* postcursor2 L3 */
  240. {
  241. {0x20, 0x20, 0x20, 0x40},
  242. {0x30, 0x30, 0x40},
  243. {0x40, 0x40},
  244. {0x60},
  245. },
  246. };
  247. enum {
  248. DRIVECURRENT_LEVEL0 = 0,
  249. DRIVECURRENT_LEVEL1 = 1,
  250. DRIVECURRENT_LEVEL2 = 2,
  251. DRIVECURRENT_LEVEL3 = 3,
  252. };
  253. enum {
  254. PREEMPHASIS_DISABLED = 0,
  255. PREEMPHASIS_LEVEL1 = 1,
  256. PREEMPHASIS_LEVEL2 = 2,
  257. PREEMPHASIS_LEVEL3 = 3,
  258. };
  259. enum {
  260. POSTCURSOR2_LEVEL0 = 0,
  261. POSTCURSOR2_LEVEL1 = 1,
  262. POSTCURSOR2_LEVEL2 = 2,
  263. POSTCURSOR2_LEVEL3 = 3,
  264. POSTCURSOR2_SUPPORTED
  265. };
  266. static inline int tegra_dp_is_max_vs(u32 pe, u32 vs)
  267. {
  268. return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1;
  269. }
  270. static inline int tegra_dp_is_max_pe(u32 pe, u32 vs)
  271. {
  272. return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1;
  273. }
  274. static inline int tegra_dp_is_max_pc(u32 pc)
  275. {
  276. return (pc < POSTCURSOR2_LEVEL3) ? 0 : 1;
  277. }
  278. /* DPCD definitions which are not defined in drm_dp_helper.h */
  279. #define DP_DPCD_REV_MAJOR_SHIFT 4
  280. #define DP_DPCD_REV_MAJOR_MASK (0xf << 4)
  281. #define DP_DPCD_REV_MINOR_SHIFT 0
  282. #define DP_DPCD_REV_MINOR_MASK 0xf
  283. #define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6
  284. #define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa
  285. #define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4
  286. #define DP_MAX_LANE_COUNT_LANE_1 0x1
  287. #define DP_MAX_LANE_COUNT_LANE_2 0x2
  288. #define DP_MAX_LANE_COUNT_LANE_4 0x4
  289. #define DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (1 << 6)
  290. #define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7)
  291. #define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0
  292. #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2)
  293. #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
  294. #define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
  295. #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
  296. #define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5)
  297. #define DP_MAX_DOWNSPREAD_VAL_NONE 0
  298. #define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1
  299. #define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6)
  300. #define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1
  301. #define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1)
  302. #define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7)
  303. #define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5)
  304. #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5)
  305. #define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5)
  306. #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0
  307. #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1
  308. #define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f
  309. #define NV_DPCD_TRAINING_LANE2_3_SET2 0x110
  310. #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2)
  311. #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0 << 2)
  312. #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6)
  313. #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0 << 6)
  314. #define NV_DPCD_LANEX_SET2_PC2_SHIFT 0
  315. #define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4
  316. #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
  317. #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
  318. #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
  319. #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
  320. #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
  321. #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
  322. #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
  323. #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
  324. #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
  325. #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
  326. #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
  327. #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
  328. #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
  329. #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
  330. #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
  331. #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
  332. #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
  333. #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
  334. #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204)
  335. #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000)
  336. #define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001)
  337. #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0
  338. #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000)
  339. #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001)
  340. #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1
  341. #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1)
  342. #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1)
  343. #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2
  344. #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2)
  345. #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2)
  346. #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4
  347. #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4)
  348. #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4)
  349. #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
  350. #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5)
  351. #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5)
  352. #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6
  353. #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6)
  354. #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
  355. #define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0
  356. #define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3
  357. #define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2
  358. #define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2)
  359. #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4
  360. #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4)
  361. #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6
  362. #define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6)
  363. #define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C)
  364. #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3
  365. #define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2)
  366. #define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E)
  367. #define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
  368. #endif