rtl8169.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * rtl8169.c : U-Boot driver for the RealTek RTL8169
  4. *
  5. * Masami Komiya (mkomiya@sonare.it)
  6. *
  7. * Most part is taken from r8169.c of etherboot
  8. *
  9. */
  10. /**************************************************************************
  11. * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
  12. * Written 2003 by Timothy Legge <tlegge@rogers.com>
  13. *
  14. * Portions of this code based on:
  15. * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
  16. * for Linux kernel 2.4.x.
  17. *
  18. * Written 2002 ShuChen <shuchen@realtek.com.tw>
  19. * See Linux Driver for full information
  20. *
  21. * Linux Driver Version 1.27a, 10.02.2002
  22. *
  23. * Thanks to:
  24. * Jean Chen of RealTek Semiconductor Corp. for
  25. * providing the evaluation NIC used to develop
  26. * this driver. RealTek's support for Etherboot
  27. * is appreciated.
  28. *
  29. * REVISION HISTORY:
  30. * ================
  31. *
  32. * v1.0 11-26-2003 timlegge Initial port of Linux driver
  33. * v1.5 01-17-2004 timlegge Initial driver output cleanup
  34. *
  35. * Indent Options: indent -kr -i8
  36. ***************************************************************************/
  37. /*
  38. * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
  39. * Modified to use le32_to_cpu and cpu_to_le32 properly
  40. */
  41. #include <common.h>
  42. #include <dm.h>
  43. #include <errno.h>
  44. #include <malloc.h>
  45. #include <memalign.h>
  46. #include <net.h>
  47. #ifndef CONFIG_DM_ETH
  48. #include <netdev.h>
  49. #endif
  50. #include <asm/io.h>
  51. #include <pci.h>
  52. #undef DEBUG_RTL8169
  53. #undef DEBUG_RTL8169_TX
  54. #undef DEBUG_RTL8169_RX
  55. #define drv_version "v1.5"
  56. #define drv_date "01-17-2004"
  57. static unsigned long ioaddr;
  58. /* Condensed operations for readability. */
  59. #define currticks() get_timer(0)
  60. /* media options */
  61. #define MAX_UNITS 8
  62. static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  63. /* MAC address length*/
  64. #define MAC_ADDR_LEN 6
  65. /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
  66. #define MAX_ETH_FRAME_SIZE 1536
  67. #define TX_FIFO_THRESH 256 /* In bytes */
  68. #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  69. #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  70. #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  71. #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
  72. #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
  73. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  74. #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
  75. #ifdef CONFIG_SYS_RX_ETH_BUFFER
  76. #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
  77. #else
  78. #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
  79. #endif
  80. #define RX_BUF_SIZE 1536 /* Rx Buffer size */
  81. #define RX_BUF_LEN 8192
  82. #define RTL_MIN_IO_SIZE 0x80
  83. #define TX_TIMEOUT (6*HZ)
  84. /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
  85. #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
  86. #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
  87. #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
  88. #define RTL_R8(reg) readb(ioaddr + (reg))
  89. #define RTL_R16(reg) readw(ioaddr + (reg))
  90. #define RTL_R32(reg) readl(ioaddr + (reg))
  91. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
  92. (pci_addr_t)(unsigned long)a)
  93. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \
  94. (phys_addr_t)a)
  95. enum RTL8169_registers {
  96. MAC0 = 0, /* Ethernet hardware address. */
  97. MAR0 = 8, /* Multicast filter. */
  98. TxDescStartAddrLow = 0x20,
  99. TxDescStartAddrHigh = 0x24,
  100. TxHDescStartAddrLow = 0x28,
  101. TxHDescStartAddrHigh = 0x2c,
  102. FLASH = 0x30,
  103. ERSR = 0x36,
  104. ChipCmd = 0x37,
  105. TxPoll = 0x38,
  106. IntrMask = 0x3C,
  107. IntrStatus = 0x3E,
  108. TxConfig = 0x40,
  109. RxConfig = 0x44,
  110. RxMissed = 0x4C,
  111. Cfg9346 = 0x50,
  112. Config0 = 0x51,
  113. Config1 = 0x52,
  114. Config2 = 0x53,
  115. Config3 = 0x54,
  116. Config4 = 0x55,
  117. Config5 = 0x56,
  118. MultiIntr = 0x5C,
  119. PHYAR = 0x60,
  120. TBICSR = 0x64,
  121. TBI_ANAR = 0x68,
  122. TBI_LPAR = 0x6A,
  123. PHYstatus = 0x6C,
  124. RxMaxSize = 0xDA,
  125. CPlusCmd = 0xE0,
  126. RxDescStartAddrLow = 0xE4,
  127. RxDescStartAddrHigh = 0xE8,
  128. EarlyTxThres = 0xEC,
  129. FuncEvent = 0xF0,
  130. FuncEventMask = 0xF4,
  131. FuncPresetState = 0xF8,
  132. FuncForceEvent = 0xFC,
  133. };
  134. enum RTL8169_register_content {
  135. /*InterruptStatusBits */
  136. SYSErr = 0x8000,
  137. PCSTimeout = 0x4000,
  138. SWInt = 0x0100,
  139. TxDescUnavail = 0x80,
  140. RxFIFOOver = 0x40,
  141. RxUnderrun = 0x20,
  142. RxOverflow = 0x10,
  143. TxErr = 0x08,
  144. TxOK = 0x04,
  145. RxErr = 0x02,
  146. RxOK = 0x01,
  147. /*RxStatusDesc */
  148. RxRES = 0x00200000,
  149. RxCRC = 0x00080000,
  150. RxRUNT = 0x00100000,
  151. RxRWT = 0x00400000,
  152. /*ChipCmdBits */
  153. CmdReset = 0x10,
  154. CmdRxEnb = 0x08,
  155. CmdTxEnb = 0x04,
  156. RxBufEmpty = 0x01,
  157. /*Cfg9346Bits */
  158. Cfg9346_Lock = 0x00,
  159. Cfg9346_Unlock = 0xC0,
  160. /*rx_mode_bits */
  161. AcceptErr = 0x20,
  162. AcceptRunt = 0x10,
  163. AcceptBroadcast = 0x08,
  164. AcceptMulticast = 0x04,
  165. AcceptMyPhys = 0x02,
  166. AcceptAllPhys = 0x01,
  167. /*RxConfigBits */
  168. RxCfgFIFOShift = 13,
  169. RxCfgDMAShift = 8,
  170. /*TxConfigBits */
  171. TxInterFrameGapShift = 24,
  172. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  173. /*rtl8169_PHYstatus */
  174. TBI_Enable = 0x80,
  175. TxFlowCtrl = 0x40,
  176. RxFlowCtrl = 0x20,
  177. _1000bpsF = 0x10,
  178. _100bps = 0x08,
  179. _10bps = 0x04,
  180. LinkStatus = 0x02,
  181. FullDup = 0x01,
  182. /*GIGABIT_PHY_registers */
  183. PHY_CTRL_REG = 0,
  184. PHY_STAT_REG = 1,
  185. PHY_AUTO_NEGO_REG = 4,
  186. PHY_1000_CTRL_REG = 9,
  187. /*GIGABIT_PHY_REG_BIT */
  188. PHY_Restart_Auto_Nego = 0x0200,
  189. PHY_Enable_Auto_Nego = 0x1000,
  190. /* PHY_STAT_REG = 1; */
  191. PHY_Auto_Nego_Comp = 0x0020,
  192. /* PHY_AUTO_NEGO_REG = 4; */
  193. PHY_Cap_10_Half = 0x0020,
  194. PHY_Cap_10_Full = 0x0040,
  195. PHY_Cap_100_Half = 0x0080,
  196. PHY_Cap_100_Full = 0x0100,
  197. /* PHY_1000_CTRL_REG = 9; */
  198. PHY_Cap_1000_Full = 0x0200,
  199. PHY_Cap_Null = 0x0,
  200. /*_MediaType*/
  201. _10_Half = 0x01,
  202. _10_Full = 0x02,
  203. _100_Half = 0x04,
  204. _100_Full = 0x08,
  205. _1000_Full = 0x10,
  206. /*_TBICSRBit*/
  207. TBILinkOK = 0x02000000,
  208. };
  209. static struct {
  210. const char *name;
  211. u8 version; /* depend on RTL8169 docs */
  212. u32 RxConfigMask; /* should clear the bits supported by this chip */
  213. } rtl_chip_info[] = {
  214. {"RTL-8169", 0x00, 0xff7e1880,},
  215. {"RTL-8169", 0x04, 0xff7e1880,},
  216. {"RTL-8169", 0x00, 0xff7e1880,},
  217. {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
  218. {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
  219. {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
  220. {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
  221. {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
  222. {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
  223. {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
  224. {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
  225. {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
  226. {"RTL-8101e", 0x34, 0xff7e1880,},
  227. {"RTL-8100e", 0x32, 0xff7e1880,},
  228. };
  229. enum _DescStatusBit {
  230. OWNbit = 0x80000000,
  231. EORbit = 0x40000000,
  232. FSbit = 0x20000000,
  233. LSbit = 0x10000000,
  234. };
  235. struct TxDesc {
  236. u32 status;
  237. u32 vlan_tag;
  238. u32 buf_addr;
  239. u32 buf_Haddr;
  240. };
  241. struct RxDesc {
  242. u32 status;
  243. u32 vlan_tag;
  244. u32 buf_addr;
  245. u32 buf_Haddr;
  246. };
  247. static unsigned char rxdata[RX_BUF_LEN];
  248. #define RTL8169_DESC_SIZE 16
  249. #if ARCH_DMA_MINALIGN > 256
  250. # define RTL8169_ALIGN ARCH_DMA_MINALIGN
  251. #else
  252. # define RTL8169_ALIGN 256
  253. #endif
  254. /*
  255. * Warn if the cache-line size is larger than the descriptor size. In such
  256. * cases the driver will likely fail because the CPU needs to flush the cache
  257. * when requeuing RX buffers, therefore descriptors written by the hardware
  258. * may be discarded.
  259. *
  260. * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  261. * the driver to allocate descriptors from a pool of non-cached memory.
  262. */
  263. #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
  264. #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
  265. !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  266. #warning cache-line size is larger than descriptor size
  267. #endif
  268. #endif
  269. /*
  270. * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
  271. * descriptors point to a part of this buffer.
  272. */
  273. DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
  274. /*
  275. * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
  276. * descriptors point to a part of this buffer.
  277. */
  278. DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
  279. struct rtl8169_private {
  280. ulong iobase;
  281. void *mmio_addr; /* memory map physical address */
  282. int chipset;
  283. unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  284. unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  285. unsigned long dirty_tx;
  286. struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
  287. struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
  288. unsigned char *RxBufferRings; /* Index of Rx Buffer */
  289. unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
  290. unsigned char *Tx_skbuff[NUM_TX_DESC];
  291. } tpx;
  292. static struct rtl8169_private *tpc;
  293. static const unsigned int rtl8169_rx_config =
  294. (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
  295. static struct pci_device_id supported[] = {
  296. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
  297. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
  298. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
  299. {}
  300. };
  301. void mdio_write(int RegAddr, int value)
  302. {
  303. int i;
  304. RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
  305. udelay(1000);
  306. for (i = 2000; i > 0; i--) {
  307. /* Check if the RTL8169 has completed writing to the specified MII register */
  308. if (!(RTL_R32(PHYAR) & 0x80000000)) {
  309. break;
  310. } else {
  311. udelay(100);
  312. }
  313. }
  314. }
  315. int mdio_read(int RegAddr)
  316. {
  317. int i, value = -1;
  318. RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
  319. udelay(1000);
  320. for (i = 2000; i > 0; i--) {
  321. /* Check if the RTL8169 has completed retrieving data from the specified MII register */
  322. if (RTL_R32(PHYAR) & 0x80000000) {
  323. value = (int) (RTL_R32(PHYAR) & 0xFFFF);
  324. break;
  325. } else {
  326. udelay(100);
  327. }
  328. }
  329. return value;
  330. }
  331. static int rtl8169_init_board(unsigned long dev_iobase, const char *name)
  332. {
  333. int i;
  334. u32 tmp;
  335. #ifdef DEBUG_RTL8169
  336. printf ("%s\n", __FUNCTION__);
  337. #endif
  338. ioaddr = dev_iobase;
  339. /* Soft reset the chip. */
  340. RTL_W8(ChipCmd, CmdReset);
  341. /* Check that the chip has finished the reset. */
  342. for (i = 1000; i > 0; i--)
  343. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  344. break;
  345. else
  346. udelay(10);
  347. /* identify chip attached to board */
  348. tmp = RTL_R32(TxConfig);
  349. tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
  350. for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
  351. if (tmp == rtl_chip_info[i].version) {
  352. tpc->chipset = i;
  353. goto match;
  354. }
  355. }
  356. /* if unknown chip, assume array element #0, original RTL-8169 in this case */
  357. printf("PCI device %s: unknown chip version, assuming RTL-8169\n",
  358. name);
  359. printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
  360. tpc->chipset = 0;
  361. match:
  362. return 0;
  363. }
  364. /*
  365. * TX and RX descriptors are 16 bytes. This causes problems with the cache
  366. * maintenance on CPUs where the cache-line size exceeds the size of these
  367. * descriptors. What will happen is that when the driver receives a packet
  368. * it will be immediately requeued for the hardware to reuse. The CPU will
  369. * therefore need to flush the cache-line containing the descriptor, which
  370. * will cause all other descriptors in the same cache-line to be flushed
  371. * along with it. If one of those descriptors had been written to by the
  372. * device those changes (and the associated packet) will be lost.
  373. *
  374. * To work around this, we make use of non-cached memory if available. If
  375. * descriptors are mapped uncached there's no need to manually flush them
  376. * or invalidate them.
  377. *
  378. * Note that this only applies to descriptors. The packet data buffers do
  379. * not have the same constraints since they are 1536 bytes large, so they
  380. * are unlikely to share cache-lines.
  381. */
  382. static void *rtl_alloc_descs(unsigned int num)
  383. {
  384. size_t size = num * RTL8169_DESC_SIZE;
  385. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  386. return (void *)noncached_alloc(size, RTL8169_ALIGN);
  387. #else
  388. return memalign(RTL8169_ALIGN, size);
  389. #endif
  390. }
  391. /*
  392. * Cache maintenance functions. These are simple wrappers around the more
  393. * general purpose flush_cache() and invalidate_dcache_range() functions.
  394. */
  395. static void rtl_inval_rx_desc(struct RxDesc *desc)
  396. {
  397. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  398. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  399. unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
  400. invalidate_dcache_range(start, end);
  401. #endif
  402. }
  403. static void rtl_flush_rx_desc(struct RxDesc *desc)
  404. {
  405. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  406. flush_cache((unsigned long)desc, sizeof(*desc));
  407. #endif
  408. }
  409. static void rtl_inval_tx_desc(struct TxDesc *desc)
  410. {
  411. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  412. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  413. unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
  414. invalidate_dcache_range(start, end);
  415. #endif
  416. }
  417. static void rtl_flush_tx_desc(struct TxDesc *desc)
  418. {
  419. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  420. flush_cache((unsigned long)desc, sizeof(*desc));
  421. #endif
  422. }
  423. static void rtl_inval_buffer(void *buf, size_t size)
  424. {
  425. unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
  426. unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
  427. invalidate_dcache_range(start, end);
  428. }
  429. static void rtl_flush_buffer(void *buf, size_t size)
  430. {
  431. flush_cache((unsigned long)buf, size);
  432. }
  433. /**************************************************************************
  434. RECV - Receive a frame
  435. ***************************************************************************/
  436. #ifdef CONFIG_DM_ETH
  437. static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
  438. uchar **packetp)
  439. #else
  440. static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
  441. uchar **packetp)
  442. #endif
  443. {
  444. /* return true if there's an ethernet packet ready to read */
  445. /* nic->packet should contain data on return */
  446. /* nic->packetlen should contain length of data */
  447. int cur_rx;
  448. int length = 0;
  449. #ifdef DEBUG_RTL8169_RX
  450. printf ("%s\n", __FUNCTION__);
  451. #endif
  452. ioaddr = dev_iobase;
  453. cur_rx = tpc->cur_rx;
  454. rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
  455. if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
  456. if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
  457. length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
  458. status) & 0x00001FFF) - 4;
  459. rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
  460. memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
  461. if (cur_rx == NUM_RX_DESC - 1)
  462. tpc->RxDescArray[cur_rx].status =
  463. cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
  464. else
  465. tpc->RxDescArray[cur_rx].status =
  466. cpu_to_le32(OWNbit + RX_BUF_SIZE);
  467. #ifdef CONFIG_DM_ETH
  468. tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
  469. dm_pci_mem_to_phys(dev,
  470. (pci_addr_t)(unsigned long)
  471. tpc->RxBufferRing[cur_rx]));
  472. #else
  473. tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
  474. pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
  475. tpc->RxBufferRing[cur_rx]));
  476. #endif
  477. rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
  478. #ifdef CONFIG_DM_ETH
  479. *packetp = rxdata;
  480. #else
  481. net_process_received_packet(rxdata, length);
  482. #endif
  483. } else {
  484. puts("Error Rx");
  485. length = -EIO;
  486. }
  487. cur_rx = (cur_rx + 1) % NUM_RX_DESC;
  488. tpc->cur_rx = cur_rx;
  489. return length;
  490. } else {
  491. ushort sts = RTL_R8(IntrStatus);
  492. RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
  493. udelay(100); /* wait */
  494. }
  495. tpc->cur_rx = cur_rx;
  496. return (0); /* initially as this is called to flush the input */
  497. }
  498. #ifdef CONFIG_DM_ETH
  499. int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  500. {
  501. struct rtl8169_private *priv = dev_get_priv(dev);
  502. return rtl_recv_common(dev, priv->iobase, packetp);
  503. }
  504. #else
  505. static int rtl_recv(struct eth_device *dev)
  506. {
  507. return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
  508. dev->iobase, NULL);
  509. }
  510. #endif /* nCONFIG_DM_ETH */
  511. #define HZ 1000
  512. /**************************************************************************
  513. SEND - Transmit a frame
  514. ***************************************************************************/
  515. #ifdef CONFIG_DM_ETH
  516. static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
  517. void *packet, int length)
  518. #else
  519. static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
  520. void *packet, int length)
  521. #endif
  522. {
  523. /* send the packet to destination */
  524. u32 to;
  525. u8 *ptxb;
  526. int entry = tpc->cur_tx % NUM_TX_DESC;
  527. u32 len = length;
  528. int ret;
  529. #ifdef DEBUG_RTL8169_TX
  530. int stime = currticks();
  531. printf ("%s\n", __FUNCTION__);
  532. printf("sending %d bytes\n", len);
  533. #endif
  534. ioaddr = dev_iobase;
  535. /* point to the current txb incase multiple tx_rings are used */
  536. ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
  537. memcpy(ptxb, (char *)packet, (int)length);
  538. while (len < ETH_ZLEN)
  539. ptxb[len++] = '\0';
  540. rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
  541. tpc->TxDescArray[entry].buf_Haddr = 0;
  542. #ifdef CONFIG_DM_ETH
  543. tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
  544. dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
  545. #else
  546. tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
  547. pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
  548. #endif
  549. if (entry != (NUM_TX_DESC - 1)) {
  550. tpc->TxDescArray[entry].status =
  551. cpu_to_le32((OWNbit | FSbit | LSbit) |
  552. ((len > ETH_ZLEN) ? len : ETH_ZLEN));
  553. } else {
  554. tpc->TxDescArray[entry].status =
  555. cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
  556. ((len > ETH_ZLEN) ? len : ETH_ZLEN));
  557. }
  558. rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
  559. RTL_W8(TxPoll, 0x40); /* set polling bit */
  560. tpc->cur_tx++;
  561. to = currticks() + TX_TIMEOUT;
  562. do {
  563. rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
  564. } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
  565. && (currticks() < to)); /* wait */
  566. if (currticks() >= to) {
  567. #ifdef DEBUG_RTL8169_TX
  568. puts("tx timeout/error\n");
  569. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  570. #endif
  571. ret = -ETIMEDOUT;
  572. } else {
  573. #ifdef DEBUG_RTL8169_TX
  574. puts("tx done\n");
  575. #endif
  576. ret = 0;
  577. }
  578. /* Delay to make net console (nc) work properly */
  579. udelay(20);
  580. return ret;
  581. }
  582. #ifdef CONFIG_DM_ETH
  583. int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
  584. {
  585. struct rtl8169_private *priv = dev_get_priv(dev);
  586. return rtl_send_common(dev, priv->iobase, packet, length);
  587. }
  588. #else
  589. static int rtl_send(struct eth_device *dev, void *packet, int length)
  590. {
  591. return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
  592. dev->iobase, packet, length);
  593. }
  594. #endif
  595. static void rtl8169_set_rx_mode(void)
  596. {
  597. u32 mc_filter[2]; /* Multicast hash filter */
  598. int rx_mode;
  599. u32 tmp = 0;
  600. #ifdef DEBUG_RTL8169
  601. printf ("%s\n", __FUNCTION__);
  602. #endif
  603. /* IFF_ALLMULTI */
  604. /* Too many to filter perfectly -- accept all multicasts. */
  605. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  606. mc_filter[1] = mc_filter[0] = 0xffffffff;
  607. tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
  608. rtl_chip_info[tpc->chipset].RxConfigMask);
  609. RTL_W32(RxConfig, tmp);
  610. RTL_W32(MAR0 + 0, mc_filter[0]);
  611. RTL_W32(MAR0 + 4, mc_filter[1]);
  612. }
  613. #ifdef CONFIG_DM_ETH
  614. static void rtl8169_hw_start(struct udevice *dev)
  615. #else
  616. static void rtl8169_hw_start(pci_dev_t dev)
  617. #endif
  618. {
  619. u32 i;
  620. #ifdef DEBUG_RTL8169
  621. int stime = currticks();
  622. printf ("%s\n", __FUNCTION__);
  623. #endif
  624. #if 0
  625. /* Soft reset the chip. */
  626. RTL_W8(ChipCmd, CmdReset);
  627. /* Check that the chip has finished the reset. */
  628. for (i = 1000; i > 0; i--) {
  629. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  630. break;
  631. else
  632. udelay(10);
  633. }
  634. #endif
  635. RTL_W8(Cfg9346, Cfg9346_Unlock);
  636. /* RTL-8169sb/8110sb or previous version */
  637. if (tpc->chipset <= 5)
  638. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  639. RTL_W8(EarlyTxThres, EarlyTxThld);
  640. /* For gigabit rtl8169 */
  641. RTL_W16(RxMaxSize, RxPacketMaxSize);
  642. /* Set Rx Config register */
  643. i = rtl8169_rx_config | (RTL_R32(RxConfig) &
  644. rtl_chip_info[tpc->chipset].RxConfigMask);
  645. RTL_W32(RxConfig, i);
  646. /* Set DMA burst size and Interframe Gap Time */
  647. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  648. (InterFrameGap << TxInterFrameGapShift));
  649. tpc->cur_rx = 0;
  650. #ifdef CONFIG_DM_ETH
  651. RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
  652. (pci_addr_t)(unsigned long)tpc->TxDescArray));
  653. #else
  654. RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
  655. (pci_addr_t)(unsigned long)tpc->TxDescArray));
  656. #endif
  657. RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
  658. #ifdef CONFIG_DM_ETH
  659. RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
  660. dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
  661. #else
  662. RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
  663. dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
  664. #endif
  665. RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
  666. /* RTL-8169sc/8110sc or later version */
  667. if (tpc->chipset > 5)
  668. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  669. RTL_W8(Cfg9346, Cfg9346_Lock);
  670. udelay(10);
  671. RTL_W32(RxMissed, 0);
  672. rtl8169_set_rx_mode();
  673. /* no early-rx interrupts */
  674. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  675. #ifdef DEBUG_RTL8169
  676. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  677. #endif
  678. }
  679. #ifdef CONFIG_DM_ETH
  680. static void rtl8169_init_ring(struct udevice *dev)
  681. #else
  682. static void rtl8169_init_ring(pci_dev_t dev)
  683. #endif
  684. {
  685. int i;
  686. #ifdef DEBUG_RTL8169
  687. int stime = currticks();
  688. printf ("%s\n", __FUNCTION__);
  689. #endif
  690. tpc->cur_rx = 0;
  691. tpc->cur_tx = 0;
  692. tpc->dirty_tx = 0;
  693. memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
  694. memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
  695. for (i = 0; i < NUM_TX_DESC; i++) {
  696. tpc->Tx_skbuff[i] = &txb[i];
  697. }
  698. for (i = 0; i < NUM_RX_DESC; i++) {
  699. if (i == (NUM_RX_DESC - 1))
  700. tpc->RxDescArray[i].status =
  701. cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
  702. else
  703. tpc->RxDescArray[i].status =
  704. cpu_to_le32(OWNbit + RX_BUF_SIZE);
  705. tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
  706. #ifdef CONFIG_DM_ETH
  707. tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
  708. dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
  709. #else
  710. tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
  711. dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
  712. #endif
  713. rtl_flush_rx_desc(&tpc->RxDescArray[i]);
  714. }
  715. #ifdef DEBUG_RTL8169
  716. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  717. #endif
  718. }
  719. #ifdef CONFIG_DM_ETH
  720. static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
  721. unsigned long dev_iobase)
  722. #else
  723. static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
  724. unsigned long dev_iobase)
  725. #endif
  726. {
  727. int i;
  728. #ifdef DEBUG_RTL8169
  729. int stime = currticks();
  730. printf ("%s\n", __FUNCTION__);
  731. #endif
  732. ioaddr = dev_iobase;
  733. rtl8169_init_ring(dev);
  734. rtl8169_hw_start(dev);
  735. /* Construct a perfect filter frame with the mac address as first match
  736. * and broadcast for all others */
  737. for (i = 0; i < 192; i++)
  738. txb[i] = 0xFF;
  739. txb[0] = enetaddr[0];
  740. txb[1] = enetaddr[1];
  741. txb[2] = enetaddr[2];
  742. txb[3] = enetaddr[3];
  743. txb[4] = enetaddr[4];
  744. txb[5] = enetaddr[5];
  745. #ifdef DEBUG_RTL8169
  746. printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
  747. #endif
  748. }
  749. #ifdef CONFIG_DM_ETH
  750. static int rtl8169_eth_start(struct udevice *dev)
  751. {
  752. struct eth_pdata *plat = dev_get_platdata(dev);
  753. struct rtl8169_private *priv = dev_get_priv(dev);
  754. rtl8169_common_start(dev, plat->enetaddr, priv->iobase);
  755. return 0;
  756. }
  757. #else
  758. /**************************************************************************
  759. RESET - Finish setting up the ethernet interface
  760. ***************************************************************************/
  761. static int rtl_reset(struct eth_device *dev, bd_t *bis)
  762. {
  763. rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
  764. dev->enetaddr, dev->iobase);
  765. return 0;
  766. }
  767. #endif /* nCONFIG_DM_ETH */
  768. static void rtl_halt_common(unsigned long dev_iobase)
  769. {
  770. int i;
  771. #ifdef DEBUG_RTL8169
  772. printf ("%s\n", __FUNCTION__);
  773. #endif
  774. ioaddr = dev_iobase;
  775. /* Stop the chip's Tx and Rx DMA processes. */
  776. RTL_W8(ChipCmd, 0x00);
  777. /* Disable interrupts by clearing the interrupt mask. */
  778. RTL_W16(IntrMask, 0x0000);
  779. RTL_W32(RxMissed, 0);
  780. for (i = 0; i < NUM_RX_DESC; i++) {
  781. tpc->RxBufferRing[i] = NULL;
  782. }
  783. }
  784. #ifdef CONFIG_DM_ETH
  785. void rtl8169_eth_stop(struct udevice *dev)
  786. {
  787. struct rtl8169_private *priv = dev_get_priv(dev);
  788. rtl_halt_common(priv->iobase);
  789. }
  790. #else
  791. /**************************************************************************
  792. HALT - Turn off ethernet interface
  793. ***************************************************************************/
  794. static void rtl_halt(struct eth_device *dev)
  795. {
  796. rtl_halt_common(dev->iobase);
  797. }
  798. #endif
  799. /**************************************************************************
  800. INIT - Look for an adapter, this routine's visible to the outside
  801. ***************************************************************************/
  802. #define board_found 1
  803. #define valid_link 0
  804. static int rtl_init(unsigned long dev_ioaddr, const char *name,
  805. unsigned char *enetaddr)
  806. {
  807. static int board_idx = -1;
  808. int i, rc;
  809. int option = -1, Cap10_100 = 0, Cap1000 = 0;
  810. #ifdef DEBUG_RTL8169
  811. printf ("%s\n", __FUNCTION__);
  812. #endif
  813. ioaddr = dev_ioaddr;
  814. board_idx++;
  815. /* point to private storage */
  816. tpc = &tpx;
  817. rc = rtl8169_init_board(ioaddr, name);
  818. if (rc)
  819. return rc;
  820. /* Get MAC address. FIXME: read EEPROM */
  821. for (i = 0; i < MAC_ADDR_LEN; i++)
  822. enetaddr[i] = RTL_R8(MAC0 + i);
  823. #ifdef DEBUG_RTL8169
  824. printf("chipset = %d\n", tpc->chipset);
  825. printf("MAC Address");
  826. for (i = 0; i < MAC_ADDR_LEN; i++)
  827. printf(":%02x", enetaddr[i]);
  828. putc('\n');
  829. #endif
  830. #ifdef DEBUG_RTL8169
  831. /* Print out some hardware info */
  832. printf("%s: at ioaddr 0x%lx\n", name, ioaddr);
  833. #endif
  834. /* if TBI is not endbled */
  835. if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
  836. int val = mdio_read(PHY_AUTO_NEGO_REG);
  837. option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
  838. /* Force RTL8169 in 10/100/1000 Full/Half mode. */
  839. if (option > 0) {
  840. #ifdef DEBUG_RTL8169
  841. printf("%s: Force-mode Enabled.\n", name);
  842. #endif
  843. Cap10_100 = 0, Cap1000 = 0;
  844. switch (option) {
  845. case _10_Half:
  846. Cap10_100 = PHY_Cap_10_Half;
  847. Cap1000 = PHY_Cap_Null;
  848. break;
  849. case _10_Full:
  850. Cap10_100 = PHY_Cap_10_Full;
  851. Cap1000 = PHY_Cap_Null;
  852. break;
  853. case _100_Half:
  854. Cap10_100 = PHY_Cap_100_Half;
  855. Cap1000 = PHY_Cap_Null;
  856. break;
  857. case _100_Full:
  858. Cap10_100 = PHY_Cap_100_Full;
  859. Cap1000 = PHY_Cap_Null;
  860. break;
  861. case _1000_Full:
  862. Cap10_100 = PHY_Cap_Null;
  863. Cap1000 = PHY_Cap_1000_Full;
  864. break;
  865. default:
  866. break;
  867. }
  868. mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
  869. mdio_write(PHY_1000_CTRL_REG, Cap1000);
  870. } else {
  871. #ifdef DEBUG_RTL8169
  872. printf("%s: Auto-negotiation Enabled.\n",
  873. name);
  874. #endif
  875. /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
  876. mdio_write(PHY_AUTO_NEGO_REG,
  877. PHY_Cap_10_Half | PHY_Cap_10_Full |
  878. PHY_Cap_100_Half | PHY_Cap_100_Full |
  879. (val & 0x1F));
  880. /* enable 1000 Full Mode */
  881. mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
  882. }
  883. /* Enable auto-negotiation and restart auto-nigotiation */
  884. mdio_write(PHY_CTRL_REG,
  885. PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
  886. udelay(100);
  887. /* wait for auto-negotiation process */
  888. for (i = 10000; i > 0; i--) {
  889. /* check if auto-negotiation complete */
  890. if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
  891. udelay(100);
  892. option = RTL_R8(PHYstatus);
  893. if (option & _1000bpsF) {
  894. #ifdef DEBUG_RTL8169
  895. printf("%s: 1000Mbps Full-duplex operation.\n",
  896. name);
  897. #endif
  898. } else {
  899. #ifdef DEBUG_RTL8169
  900. printf("%s: %sMbps %s-duplex operation.\n",
  901. name,
  902. (option & _100bps) ? "100" :
  903. "10",
  904. (option & FullDup) ? "Full" :
  905. "Half");
  906. #endif
  907. }
  908. break;
  909. } else {
  910. udelay(100);
  911. }
  912. } /* end for-loop to wait for auto-negotiation process */
  913. } else {
  914. udelay(100);
  915. #ifdef DEBUG_RTL8169
  916. printf
  917. ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
  918. name,
  919. (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
  920. #endif
  921. }
  922. tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
  923. if (!tpc->RxDescArray)
  924. return -ENOMEM;
  925. tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
  926. if (!tpc->TxDescArray)
  927. return -ENOMEM;
  928. return 0;
  929. }
  930. #ifndef CONFIG_DM_ETH
  931. int rtl8169_initialize(bd_t *bis)
  932. {
  933. pci_dev_t devno;
  934. int card_number = 0;
  935. struct eth_device *dev;
  936. u32 iobase;
  937. int idx=0;
  938. while(1){
  939. unsigned int region;
  940. u16 device;
  941. int err;
  942. /* Find RTL8169 */
  943. if ((devno = pci_find_devices(supported, idx++)) < 0)
  944. break;
  945. pci_read_config_word(devno, PCI_DEVICE_ID, &device);
  946. switch (device) {
  947. case 0x8168:
  948. region = 2;
  949. break;
  950. default:
  951. region = 1;
  952. break;
  953. }
  954. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
  955. iobase &= ~0xf;
  956. debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
  957. dev = (struct eth_device *)malloc(sizeof *dev);
  958. if (!dev) {
  959. printf("Can not allocate memory of rtl8169\n");
  960. break;
  961. }
  962. memset(dev, 0, sizeof(*dev));
  963. sprintf (dev->name, "RTL8169#%d", card_number);
  964. dev->priv = (void *)(unsigned long)devno;
  965. dev->iobase = (int)pci_mem_to_phys(devno, iobase);
  966. dev->init = rtl_reset;
  967. dev->halt = rtl_halt;
  968. dev->send = rtl_send;
  969. dev->recv = rtl_recv;
  970. err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
  971. if (err < 0) {
  972. printf(pr_fmt("failed to initialize card: %d\n"), err);
  973. free(dev);
  974. continue;
  975. }
  976. eth_register (dev);
  977. card_number++;
  978. }
  979. return card_number;
  980. }
  981. #endif
  982. #ifdef CONFIG_DM_ETH
  983. static int rtl8169_eth_probe(struct udevice *dev)
  984. {
  985. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  986. struct rtl8169_private *priv = dev_get_priv(dev);
  987. struct eth_pdata *plat = dev_get_platdata(dev);
  988. u32 iobase;
  989. int region;
  990. int ret;
  991. debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
  992. switch (pplat->device) {
  993. case 0x8168:
  994. region = 2;
  995. break;
  996. default:
  997. region = 1;
  998. break;
  999. }
  1000. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0 + region * 4, &iobase);
  1001. iobase &= ~0xf;
  1002. priv->iobase = (int)dm_pci_mem_to_phys(dev, iobase);
  1003. ret = rtl_init(priv->iobase, dev->name, plat->enetaddr);
  1004. if (ret < 0) {
  1005. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  1006. return ret;
  1007. }
  1008. return 0;
  1009. }
  1010. static const struct eth_ops rtl8169_eth_ops = {
  1011. .start = rtl8169_eth_start,
  1012. .send = rtl8169_eth_send,
  1013. .recv = rtl8169_eth_recv,
  1014. .stop = rtl8169_eth_stop,
  1015. };
  1016. static const struct udevice_id rtl8169_eth_ids[] = {
  1017. { .compatible = "realtek,rtl8169" },
  1018. { }
  1019. };
  1020. U_BOOT_DRIVER(eth_rtl8169) = {
  1021. .name = "eth_rtl8169",
  1022. .id = UCLASS_ETH,
  1023. .of_match = rtl8169_eth_ids,
  1024. .probe = rtl8169_eth_probe,
  1025. .ops = &rtl8169_eth_ops,
  1026. .priv_auto_alloc_size = sizeof(struct rtl8169_private),
  1027. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1028. };
  1029. U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
  1030. #endif