natsemi.c 23 KB

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  1. /*
  2. natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
  3. Author: Mark A. Rakes (mark_rakes@vivato.net)
  4. Adapted from an Etherboot driver written by:
  5. Copyright (C) 2001 Entity Cyber, Inc.
  6. This development of this Etherboot driver was funded by
  7. Sicom Systems: http://www.sicompos.com/
  8. Author: Marty Connor (mdc@thinguin.org)
  9. Adapted from a Linux driver which was written by Donald Becker
  10. This software may be used and distributed according to the terms
  11. of the GNU Public License (GPL), incorporated herein by reference.
  12. Original Copyright Notice:
  13. Written/copyright 1999-2001 by Donald Becker.
  14. This software may be used and distributed according to the terms of
  15. the GNU General Public License (GPL), incorporated herein by reference.
  16. Drivers based on or derived from this code fall under the GPL and must
  17. retain the authorship, copyright and license notice. This file is not
  18. a complete program and may only be used when the entire operating
  19. system is licensed under the GPL. License for under other terms may be
  20. available. Contact the original author for details.
  21. The original author may be reached as becker@scyld.com, or at
  22. Scyld Computing Corporation
  23. 410 Severn Ave., Suite 210
  24. Annapolis MD 21403
  25. Support information and updates available at
  26. http://www.scyld.com/network/netsemi.html
  27. References:
  28. http://www.scyld.com/expert/100mbps.html
  29. http://www.scyld.com/expert/NWay.html
  30. Datasheet is available from:
  31. http://www.national.com/pf/DP/DP83815.html
  32. */
  33. /* Revision History
  34. * October 2002 mar 1.0
  35. * Initial U-Boot Release. Tested with Netgear FA311 board
  36. * and dp83815 chipset on custom board
  37. */
  38. /* Includes */
  39. #include <common.h>
  40. #include <malloc.h>
  41. #include <net.h>
  42. #include <netdev.h>
  43. #include <asm/io.h>
  44. #include <pci.h>
  45. /* defines */
  46. #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
  47. #define DSIZE 0x00000FFF
  48. #define CRC_SIZE 4
  49. #define TOUT_LOOP 500000
  50. #define TX_BUF_SIZE 1536
  51. #define RX_BUF_SIZE 1536
  52. #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
  53. /* Offsets to the device registers.
  54. Unlike software-only systems, device drivers interact with complex hardware.
  55. It's not useful to define symbolic names for every register bit in the
  56. device. */
  57. enum register_offsets {
  58. ChipCmd = 0x00,
  59. ChipConfig = 0x04,
  60. EECtrl = 0x08,
  61. IntrMask = 0x14,
  62. IntrEnable = 0x18,
  63. TxRingPtr = 0x20,
  64. TxConfig = 0x24,
  65. RxRingPtr = 0x30,
  66. RxConfig = 0x34,
  67. ClkRun = 0x3C,
  68. RxFilterAddr = 0x48,
  69. RxFilterData = 0x4C,
  70. SiliconRev = 0x58,
  71. PCIPM = 0x44,
  72. BasicControl = 0x80,
  73. BasicStatus = 0x84,
  74. /* These are from the spec, around page 78... on a separate table. */
  75. PGSEL = 0xCC,
  76. PMDCSR = 0xE4,
  77. TSTDAT = 0xFC,
  78. DSPCFG = 0xF4,
  79. SDCFG = 0x8C
  80. };
  81. /* Bit in ChipCmd. */
  82. enum ChipCmdBits {
  83. ChipReset = 0x100,
  84. RxReset = 0x20,
  85. TxReset = 0x10,
  86. RxOff = 0x08,
  87. RxOn = 0x04,
  88. TxOff = 0x02,
  89. TxOn = 0x01
  90. };
  91. enum ChipConfigBits {
  92. LinkSts = 0x80000000,
  93. HundSpeed = 0x40000000,
  94. FullDuplex = 0x20000000,
  95. TenPolarity = 0x10000000,
  96. AnegDone = 0x08000000,
  97. AnegEnBothBoth = 0x0000E000,
  98. AnegDis100Full = 0x0000C000,
  99. AnegEn100Both = 0x0000A000,
  100. AnegDis100Half = 0x00008000,
  101. AnegEnBothHalf = 0x00006000,
  102. AnegDis10Full = 0x00004000,
  103. AnegEn10Both = 0x00002000,
  104. DuplexMask = 0x00008000,
  105. SpeedMask = 0x00004000,
  106. AnegMask = 0x00002000,
  107. AnegDis10Half = 0x00000000,
  108. ExtPhy = 0x00001000,
  109. PhyRst = 0x00000400,
  110. PhyDis = 0x00000200,
  111. BootRomDisable = 0x00000004,
  112. BEMode = 0x00000001,
  113. };
  114. enum TxConfig_bits {
  115. TxDrthMask = 0x3f,
  116. TxFlthMask = 0x3f00,
  117. TxMxdmaMask = 0x700000,
  118. TxMxdma_512 = 0x0,
  119. TxMxdma_4 = 0x100000,
  120. TxMxdma_8 = 0x200000,
  121. TxMxdma_16 = 0x300000,
  122. TxMxdma_32 = 0x400000,
  123. TxMxdma_64 = 0x500000,
  124. TxMxdma_128 = 0x600000,
  125. TxMxdma_256 = 0x700000,
  126. TxCollRetry = 0x800000,
  127. TxAutoPad = 0x10000000,
  128. TxMacLoop = 0x20000000,
  129. TxHeartIgn = 0x40000000,
  130. TxCarrierIgn = 0x80000000
  131. };
  132. enum RxConfig_bits {
  133. RxDrthMask = 0x3e,
  134. RxMxdmaMask = 0x700000,
  135. RxMxdma_512 = 0x0,
  136. RxMxdma_4 = 0x100000,
  137. RxMxdma_8 = 0x200000,
  138. RxMxdma_16 = 0x300000,
  139. RxMxdma_32 = 0x400000,
  140. RxMxdma_64 = 0x500000,
  141. RxMxdma_128 = 0x600000,
  142. RxMxdma_256 = 0x700000,
  143. RxAcceptLong = 0x8000000,
  144. RxAcceptTx = 0x10000000,
  145. RxAcceptRunt = 0x40000000,
  146. RxAcceptErr = 0x80000000
  147. };
  148. /* Bits in the RxMode register. */
  149. enum rx_mode_bits {
  150. AcceptErr = 0x20,
  151. AcceptRunt = 0x10,
  152. AcceptBroadcast = 0xC0000000,
  153. AcceptMulticast = 0x00200000,
  154. AcceptAllMulticast = 0x20000000,
  155. AcceptAllPhys = 0x10000000,
  156. AcceptMyPhys = 0x08000000
  157. };
  158. typedef struct _BufferDesc {
  159. u32 link;
  160. vu_long cmdsts;
  161. u32 bufptr;
  162. u32 software_use;
  163. } BufferDesc;
  164. /* Bits in network_desc.status */
  165. enum desc_status_bits {
  166. DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
  167. DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
  168. DescSizeMask = 0xfff,
  169. DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
  170. DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
  171. DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
  172. DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
  173. DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
  174. DescRxDest = 0x01800000, DescRxLong = 0x00400000,
  175. DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
  176. DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
  177. DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
  178. };
  179. /* Globals */
  180. #ifdef NATSEMI_DEBUG
  181. static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
  182. #endif
  183. static u32 SavedClkRun;
  184. static unsigned int cur_rx;
  185. static unsigned int advertising;
  186. static unsigned int rx_config;
  187. static unsigned int tx_config;
  188. /* Note: transmit and receive buffers and descriptors must be
  189. longword aligned */
  190. static BufferDesc txd __attribute__ ((aligned(4)));
  191. static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
  192. static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
  193. static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
  194. __attribute__ ((aligned(4)));
  195. /* Function Prototypes */
  196. #if 0
  197. static void write_eeprom(struct eth_device *dev, long addr, int location,
  198. short value);
  199. #endif
  200. static int read_eeprom(struct eth_device *dev, long addr, int location);
  201. static int mdio_read(struct eth_device *dev, int phy_id, int location);
  202. static int natsemi_init(struct eth_device *dev, bd_t * bis);
  203. static void natsemi_reset(struct eth_device *dev);
  204. static void natsemi_init_rxfilter(struct eth_device *dev);
  205. static void natsemi_init_txd(struct eth_device *dev);
  206. static void natsemi_init_rxd(struct eth_device *dev);
  207. static void natsemi_set_rx_mode(struct eth_device *dev);
  208. static void natsemi_check_duplex(struct eth_device *dev);
  209. static int natsemi_send(struct eth_device *dev, void *packet, int length);
  210. static int natsemi_poll(struct eth_device *dev);
  211. static void natsemi_disable(struct eth_device *dev);
  212. static struct pci_device_id supported[] = {
  213. {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
  214. {}
  215. };
  216. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  217. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  218. static inline int
  219. INW(struct eth_device *dev, u_long addr)
  220. {
  221. return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
  222. }
  223. static int
  224. INL(struct eth_device *dev, u_long addr)
  225. {
  226. return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
  227. }
  228. static inline void
  229. OUTW(struct eth_device *dev, int command, u_long addr)
  230. {
  231. *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
  232. }
  233. static inline void
  234. OUTL(struct eth_device *dev, int command, u_long addr)
  235. {
  236. *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
  237. }
  238. /*
  239. * Function: natsemi_initialize
  240. *
  241. * Description: Retrieves the MAC address of the card, and sets up some
  242. * globals required by other routines, and initializes the NIC, making it
  243. * ready to send and receive packets.
  244. *
  245. * Side effects:
  246. * leaves the natsemi initialized, and ready to receive packets.
  247. *
  248. * Returns: struct eth_device *: pointer to NIC data structure
  249. */
  250. int
  251. natsemi_initialize(bd_t * bis)
  252. {
  253. pci_dev_t devno;
  254. int card_number = 0;
  255. struct eth_device *dev;
  256. u32 iobase, status, chip_config;
  257. int i, idx = 0;
  258. int prev_eedata;
  259. u32 tmp;
  260. while (1) {
  261. /* Find PCI device(s) */
  262. if ((devno = pci_find_devices(supported, idx++)) < 0) {
  263. break;
  264. }
  265. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
  266. iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
  267. pci_write_config_dword(devno, PCI_COMMAND,
  268. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  269. /* Check if I/O accesses and Bus Mastering are enabled. */
  270. pci_read_config_dword(devno, PCI_COMMAND, &status);
  271. if (!(status & PCI_COMMAND_MEMORY)) {
  272. printf("Error: Can not enable MEM access.\n");
  273. continue;
  274. } else if (!(status & PCI_COMMAND_MASTER)) {
  275. printf("Error: Can not enable Bus Mastering.\n");
  276. continue;
  277. }
  278. dev = (struct eth_device *) malloc(sizeof *dev);
  279. if (!dev) {
  280. printf("natsemi: Can not allocate memory\n");
  281. break;
  282. }
  283. memset(dev, 0, sizeof(*dev));
  284. sprintf(dev->name, "dp83815#%d", card_number);
  285. dev->iobase = bus_to_phys(iobase);
  286. #ifdef NATSEMI_DEBUG
  287. printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
  288. #endif
  289. dev->priv = (void *) devno;
  290. dev->init = natsemi_init;
  291. dev->halt = natsemi_disable;
  292. dev->send = natsemi_send;
  293. dev->recv = natsemi_poll;
  294. eth_register(dev);
  295. card_number++;
  296. /* Set the latency timer for value. */
  297. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  298. udelay(10 * 1000);
  299. /* natsemi has a non-standard PM control register
  300. * in PCI config space. Some boards apparently need
  301. * to be brought to D0 in this manner. */
  302. pci_read_config_dword(devno, PCIPM, &tmp);
  303. if (tmp & (0x03 | 0x100)) {
  304. /* D0 state, disable PME assertion */
  305. u32 newtmp = tmp & ~(0x03 | 0x100);
  306. pci_write_config_dword(devno, PCIPM, newtmp);
  307. }
  308. printf("natsemi: EEPROM contents:\n");
  309. for (i = 0; i <= EEPROM_SIZE; i++) {
  310. short eedata = read_eeprom(dev, EECtrl, i);
  311. printf(" %04hx", eedata);
  312. }
  313. printf("\n");
  314. /* get MAC address */
  315. prev_eedata = read_eeprom(dev, EECtrl, 6);
  316. for (i = 0; i < 3; i++) {
  317. int eedata = read_eeprom(dev, EECtrl, i + 7);
  318. dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
  319. dev->enetaddr[i*2+1] = eedata >> 7;
  320. prev_eedata = eedata;
  321. }
  322. /* Reset the chip to erase any previous misconfiguration. */
  323. OUTL(dev, ChipReset, ChipCmd);
  324. advertising = mdio_read(dev, 1, 4);
  325. chip_config = INL(dev, ChipConfig);
  326. #ifdef NATSEMI_DEBUG
  327. printf("%s: Transceiver status %#08X advertising %#08X\n",
  328. dev->name, (int) INL(dev, BasicStatus), advertising);
  329. printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
  330. dev->name, chip_config & AnegMask ? "enabled, advertise" :
  331. "disabled, force", chip_config & SpeedMask ? "0" : "",
  332. chip_config & DuplexMask ? "full" : "half");
  333. #endif
  334. chip_config |= AnegEnBothBoth;
  335. #ifdef NATSEMI_DEBUG
  336. printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
  337. dev->name, chip_config & AnegMask ? "enabled, advertise" :
  338. "disabled, force", chip_config & SpeedMask ? "0" : "",
  339. chip_config & DuplexMask ? "full" : "half");
  340. #endif
  341. /*write new autoneg bits, reset phy*/
  342. OUTL(dev, (chip_config | PhyRst), ChipConfig);
  343. /*un-reset phy*/
  344. OUTL(dev, chip_config, ChipConfig);
  345. /* Disable PME:
  346. * The PME bit is initialized from the EEPROM contents.
  347. * PCI cards probably have PME disabled, but motherboard
  348. * implementations may have PME set to enable WakeOnLan.
  349. * With PME set the chip will scan incoming packets but
  350. * nothing will be written to memory. */
  351. SavedClkRun = INL(dev, ClkRun);
  352. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  353. }
  354. return card_number;
  355. }
  356. /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
  357. The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
  358. /* Delay between EEPROM clock transitions.
  359. No extra delay is needed with 33MHz PCI, but future 66MHz
  360. access may need a delay. */
  361. #define eeprom_delay(ee_addr) INL(dev, ee_addr)
  362. enum EEPROM_Ctrl_Bits {
  363. EE_ShiftClk = 0x04,
  364. EE_DataIn = 0x01,
  365. EE_ChipSelect = 0x08,
  366. EE_DataOut = 0x02
  367. };
  368. #define EE_Write0 (EE_ChipSelect)
  369. #define EE_Write1 (EE_ChipSelect | EE_DataIn)
  370. /* The EEPROM commands include the alway-set leading bit. */
  371. enum EEPROM_Cmds {
  372. EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
  373. EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
  374. };
  375. #if 0
  376. static void
  377. write_eeprom(struct eth_device *dev, long addr, int location, short value)
  378. {
  379. int i;
  380. int ee_addr = (typeof(ee_addr))addr;
  381. short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
  382. short write_cmd = location | EE_WriteCmd;
  383. #ifdef NATSEMI_DEBUG
  384. printf("write_eeprom: %08x, %04hx, %04hx\n",
  385. dev->iobase + ee_addr, write_cmd, value);
  386. #endif
  387. /* Shift the write enable command bits out. */
  388. for (i = 9; i >= 0; i--) {
  389. short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  390. OUTL(dev, cmdval, ee_addr);
  391. eeprom_delay(ee_addr);
  392. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  393. eeprom_delay(ee_addr);
  394. }
  395. OUTL(dev, 0, ee_addr); /*bring chip select low*/
  396. OUTL(dev, EE_ShiftClk, ee_addr);
  397. eeprom_delay(ee_addr);
  398. /* Shift the write command bits out. */
  399. for (i = 9; i >= 0; i--) {
  400. short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  401. OUTL(dev, cmdval, ee_addr);
  402. eeprom_delay(ee_addr);
  403. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  404. eeprom_delay(ee_addr);
  405. }
  406. for (i = 0; i < 16; i++) {
  407. short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
  408. OUTL(dev, cmdval, ee_addr);
  409. eeprom_delay(ee_addr);
  410. OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
  411. eeprom_delay(ee_addr);
  412. }
  413. OUTL(dev, 0, ee_addr); /*bring chip select low*/
  414. OUTL(dev, EE_ShiftClk, ee_addr);
  415. for (i = 0; i < 200000; i++) {
  416. OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
  417. if (INL(dev, ee_addr) & EE_DataOut) {
  418. break; /*finished*/
  419. }
  420. }
  421. eeprom_delay(ee_addr);
  422. /* Terminate the EEPROM access. */
  423. OUTL(dev, EE_Write0, ee_addr);
  424. OUTL(dev, 0, ee_addr);
  425. return;
  426. }
  427. #endif
  428. static int
  429. read_eeprom(struct eth_device *dev, long addr, int location)
  430. {
  431. int i;
  432. int retval = 0;
  433. int ee_addr = (typeof(ee_addr))addr;
  434. int read_cmd = location | EE_ReadCmd;
  435. OUTL(dev, EE_Write0, ee_addr);
  436. /* Shift the read command bits out. */
  437. for (i = 10; i >= 0; i--) {
  438. short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  439. OUTL(dev, dataval, ee_addr);
  440. eeprom_delay(ee_addr);
  441. OUTL(dev, dataval | EE_ShiftClk, ee_addr);
  442. eeprom_delay(ee_addr);
  443. }
  444. OUTL(dev, EE_ChipSelect, ee_addr);
  445. eeprom_delay(ee_addr);
  446. for (i = 0; i < 16; i++) {
  447. OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
  448. eeprom_delay(ee_addr);
  449. retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
  450. OUTL(dev, EE_ChipSelect, ee_addr);
  451. eeprom_delay(ee_addr);
  452. }
  453. /* Terminate the EEPROM access. */
  454. OUTL(dev, EE_Write0, ee_addr);
  455. OUTL(dev, 0, ee_addr);
  456. #ifdef NATSEMI_DEBUG
  457. if (natsemi_debug)
  458. printf("read_eeprom: %08x, %08x, retval %08x\n",
  459. dev->iobase + ee_addr, read_cmd, retval);
  460. #endif
  461. return retval;
  462. }
  463. /* MII transceiver control section.
  464. The 83815 series has an internal transceiver, and we present the
  465. management registers as if they were MII connected. */
  466. static int
  467. mdio_read(struct eth_device *dev, int phy_id, int location)
  468. {
  469. if (phy_id == 1 && location < 32)
  470. return INL(dev, BasicControl+(location<<2))&0xffff;
  471. else
  472. return 0xffff;
  473. }
  474. /* Function: natsemi_init
  475. *
  476. * Description: resets the ethernet controller chip and configures
  477. * registers and data structures required for sending and receiving packets.
  478. *
  479. * Arguments: struct eth_device *dev: NIC data structure
  480. *
  481. * returns: int.
  482. */
  483. static int
  484. natsemi_init(struct eth_device *dev, bd_t * bis)
  485. {
  486. natsemi_reset(dev);
  487. /* Disable PME:
  488. * The PME bit is initialized from the EEPROM contents.
  489. * PCI cards probably have PME disabled, but motherboard
  490. * implementations may have PME set to enable WakeOnLan.
  491. * With PME set the chip will scan incoming packets but
  492. * nothing will be written to memory. */
  493. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  494. natsemi_init_rxfilter(dev);
  495. natsemi_init_txd(dev);
  496. natsemi_init_rxd(dev);
  497. /* Configure the PCI bus bursts and FIFO thresholds. */
  498. tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
  499. rx_config = RxMxdma_256 | 0x20;
  500. #ifdef NATSEMI_DEBUG
  501. printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
  502. printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
  503. #endif
  504. OUTL(dev, tx_config, TxConfig);
  505. OUTL(dev, rx_config, RxConfig);
  506. natsemi_check_duplex(dev);
  507. natsemi_set_rx_mode(dev);
  508. OUTL(dev, (RxOn | TxOn), ChipCmd);
  509. return 1;
  510. }
  511. /*
  512. * Function: natsemi_reset
  513. *
  514. * Description: soft resets the controller chip
  515. *
  516. * Arguments: struct eth_device *dev: NIC data structure
  517. *
  518. * Returns: void.
  519. */
  520. static void
  521. natsemi_reset(struct eth_device *dev)
  522. {
  523. OUTL(dev, ChipReset, ChipCmd);
  524. /* On page 78 of the spec, they recommend some settings for "optimum
  525. performance" to be done in sequence. These settings optimize some
  526. of the 100Mbit autodetection circuitry. Also, we only want to do
  527. this for rev C of the chip. */
  528. if (INL(dev, SiliconRev) == 0x302) {
  529. OUTW(dev, 0x0001, PGSEL);
  530. OUTW(dev, 0x189C, PMDCSR);
  531. OUTW(dev, 0x0000, TSTDAT);
  532. OUTW(dev, 0x5040, DSPCFG);
  533. OUTW(dev, 0x008C, SDCFG);
  534. }
  535. /* Disable interrupts using the mask. */
  536. OUTL(dev, 0, IntrMask);
  537. OUTL(dev, 0, IntrEnable);
  538. }
  539. /* Function: natsemi_init_rxfilter
  540. *
  541. * Description: sets receive filter address to our MAC address
  542. *
  543. * Arguments: struct eth_device *dev: NIC data structure
  544. *
  545. * returns: void.
  546. */
  547. static void
  548. natsemi_init_rxfilter(struct eth_device *dev)
  549. {
  550. int i;
  551. for (i = 0; i < ETH_ALEN; i += 2) {
  552. OUTL(dev, i, RxFilterAddr);
  553. OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
  554. RxFilterData);
  555. }
  556. }
  557. /*
  558. * Function: natsemi_init_txd
  559. *
  560. * Description: initializes the Tx descriptor
  561. *
  562. * Arguments: struct eth_device *dev: NIC data structure
  563. *
  564. * returns: void.
  565. */
  566. static void
  567. natsemi_init_txd(struct eth_device *dev)
  568. {
  569. txd.link = (u32) 0;
  570. txd.cmdsts = (u32) 0;
  571. txd.bufptr = (u32) & txb[0];
  572. /* load Transmit Descriptor Register */
  573. OUTL(dev, (u32) & txd, TxRingPtr);
  574. #ifdef NATSEMI_DEBUG
  575. printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
  576. INL(dev, TxRingPtr));
  577. #endif
  578. }
  579. /* Function: natsemi_init_rxd
  580. *
  581. * Description: initializes the Rx descriptor ring
  582. *
  583. * Arguments: struct eth_device *dev: NIC data structure
  584. *
  585. * Returns: void.
  586. */
  587. static void
  588. natsemi_init_rxd(struct eth_device *dev)
  589. {
  590. int i;
  591. cur_rx = 0;
  592. /* init RX descriptor */
  593. for (i = 0; i < NUM_RX_DESC; i++) {
  594. rxd[i].link =
  595. cpu_to_le32((i + 1 <
  596. NUM_RX_DESC) ? (u32) & rxd[i +
  597. 1] : (u32) &
  598. rxd[0]);
  599. rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
  600. rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
  601. #ifdef NATSEMI_DEBUG
  602. printf
  603. ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
  604. i, &rxd[i], le32_to_cpu(rxd[i].link),
  605. rxd[i].cmdsts, rxd[i].bufptr);
  606. #endif
  607. }
  608. /* load Receive Descriptor Register */
  609. OUTL(dev, (u32) & rxd[0], RxRingPtr);
  610. #ifdef NATSEMI_DEBUG
  611. printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
  612. INL(dev, RxRingPtr));
  613. #endif
  614. }
  615. /* Function: natsemi_set_rx_mode
  616. *
  617. * Description:
  618. * sets the receive mode to accept all broadcast packets and packets
  619. * with our MAC address, and reject all multicast packets.
  620. *
  621. * Arguments: struct eth_device *dev: NIC data structure
  622. *
  623. * Returns: void.
  624. */
  625. static void
  626. natsemi_set_rx_mode(struct eth_device *dev)
  627. {
  628. u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
  629. OUTL(dev, rx_mode, RxFilterAddr);
  630. }
  631. static void
  632. natsemi_check_duplex(struct eth_device *dev)
  633. {
  634. int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
  635. #ifdef NATSEMI_DEBUG
  636. printf("%s: Setting %s-duplex based on negotiated link"
  637. " capability.\n", dev->name, duplex ? "full" : "half");
  638. #endif
  639. if (duplex) {
  640. rx_config |= RxAcceptTx;
  641. tx_config |= (TxCarrierIgn | TxHeartIgn);
  642. } else {
  643. rx_config &= ~RxAcceptTx;
  644. tx_config &= ~(TxCarrierIgn | TxHeartIgn);
  645. }
  646. OUTL(dev, tx_config, TxConfig);
  647. OUTL(dev, rx_config, RxConfig);
  648. }
  649. /* Function: natsemi_send
  650. *
  651. * Description: transmits a packet and waits for completion or timeout.
  652. *
  653. * Returns: void. */
  654. static int natsemi_send(struct eth_device *dev, void *packet, int length)
  655. {
  656. u32 i, status = 0;
  657. u32 tx_status = 0;
  658. u32 *tx_ptr = &tx_status;
  659. vu_long *res = (vu_long *)tx_ptr;
  660. /* Stop the transmitter */
  661. OUTL(dev, TxOff, ChipCmd);
  662. #ifdef NATSEMI_DEBUG
  663. if (natsemi_debug)
  664. printf("natsemi_send: sending %d bytes\n", (int) length);
  665. #endif
  666. /* set the transmit buffer descriptor and enable Transmit State Machine */
  667. txd.link = cpu_to_le32(0);
  668. txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
  669. txd.cmdsts = cpu_to_le32(DescOwn | length);
  670. /* load Transmit Descriptor Register */
  671. OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
  672. #ifdef NATSEMI_DEBUG
  673. if (natsemi_debug)
  674. printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
  675. INL(dev, TxRingPtr));
  676. #endif
  677. /* restart the transmitter */
  678. OUTL(dev, TxOn, ChipCmd);
  679. for (i = 0;
  680. (*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
  681. i++) {
  682. if (i >= TOUT_LOOP) {
  683. printf
  684. ("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
  685. dev->name, tx_status);
  686. goto Done;
  687. }
  688. }
  689. if (!(tx_status & DescPktOK)) {
  690. printf("natsemi_send: Transmit error, Tx status %X.\n",
  691. tx_status);
  692. goto Done;
  693. }
  694. status = 1;
  695. Done:
  696. return status;
  697. }
  698. /* Function: natsemi_poll
  699. *
  700. * Description: checks for a received packet and returns it if found.
  701. *
  702. * Arguments: struct eth_device *dev: NIC data structure
  703. *
  704. * Returns: 1 if packet was received.
  705. * 0 if no packet was received.
  706. *
  707. * Side effects:
  708. * Returns (copies) the packet to the array dev->packet.
  709. * Returns the length of the packet.
  710. */
  711. static int
  712. natsemi_poll(struct eth_device *dev)
  713. {
  714. int retstat = 0;
  715. int length = 0;
  716. u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
  717. if (!(rx_status & (u32) DescOwn))
  718. return retstat;
  719. #ifdef NATSEMI_DEBUG
  720. if (natsemi_debug)
  721. printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
  722. cur_rx, rx_status);
  723. #endif
  724. length = (rx_status & DSIZE) - CRC_SIZE;
  725. if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
  726. printf
  727. ("natsemi_poll: Corrupted packet received, buffer status = %X\n",
  728. rx_status);
  729. retstat = 0;
  730. } else { /* give packet to higher level routine */
  731. net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
  732. length);
  733. retstat = 1;
  734. }
  735. /* return the descriptor and buffer to receive ring */
  736. rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
  737. rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
  738. if (++cur_rx == NUM_RX_DESC)
  739. cur_rx = 0;
  740. /* re-enable the potentially idle receive state machine */
  741. OUTL(dev, RxOn, ChipCmd);
  742. return retstat;
  743. }
  744. /* Function: natsemi_disable
  745. *
  746. * Description: Turns off interrupts and stops Tx and Rx engines
  747. *
  748. * Arguments: struct eth_device *dev: NIC data structure
  749. *
  750. * Returns: void.
  751. */
  752. static void
  753. natsemi_disable(struct eth_device *dev)
  754. {
  755. /* Disable interrupts using the mask. */
  756. OUTL(dev, 0, IntrMask);
  757. OUTL(dev, 0, IntrEnable);
  758. /* Stop the chip's Tx and Rx processes. */
  759. OUTL(dev, RxOff | TxOff, ChipCmd);
  760. /* Restore PME enable bit */
  761. OUTL(dev, SavedClkRun, ClkRun);
  762. }