eepro100.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/io.h>
  11. #include <pci.h>
  12. #include <miiphy.h>
  13. #undef DEBUG
  14. /* Ethernet chip registers.
  15. */
  16. #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
  17. #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
  18. #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
  19. #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
  20. #define SCBPointer 4 /* General purpose pointer. */
  21. #define SCBPort 8 /* Misc. commands and operands. */
  22. #define SCBflash 12 /* Flash memory control. */
  23. #define SCBeeprom 14 /* EEPROM memory control. */
  24. #define SCBCtrlMDI 16 /* MDI interface control. */
  25. #define SCBEarlyRx 20 /* Early receive byte count. */
  26. #define SCBGenControl 28 /* 82559 General Control Register */
  27. #define SCBGenStatus 29 /* 82559 General Status register */
  28. /* 82559 SCB status word defnitions
  29. */
  30. #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
  31. #define SCB_STATUS_FR 0x4000 /* frame received */
  32. #define SCB_STATUS_CNA 0x2000 /* CU left active state */
  33. #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
  34. #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
  35. #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
  36. #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
  37. #define SCB_INTACK_MASK 0xFD00 /* all the above */
  38. #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
  39. #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
  40. /* System control block commands
  41. */
  42. /* CU Commands */
  43. #define CU_NOP 0x0000
  44. #define CU_START 0x0010
  45. #define CU_RESUME 0x0020
  46. #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
  47. #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
  48. #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
  49. #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
  50. /* RUC Commands */
  51. #define RUC_NOP 0x0000
  52. #define RUC_START 0x0001
  53. #define RUC_RESUME 0x0002
  54. #define RUC_ABORT 0x0004
  55. #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
  56. #define RUC_RESUMENR 0x0007
  57. #define CU_CMD_MASK 0x00f0
  58. #define RU_CMD_MASK 0x0007
  59. #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
  60. #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
  61. #define CU_STATUS_MASK 0x00C0
  62. #define RU_STATUS_MASK 0x003C
  63. #define RU_STATUS_IDLE (0<<2)
  64. #define RU_STATUS_SUS (1<<2)
  65. #define RU_STATUS_NORES (2<<2)
  66. #define RU_STATUS_READY (4<<2)
  67. #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
  68. #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
  69. #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
  70. /* 82559 Port interface commands.
  71. */
  72. #define I82559_RESET 0x00000000 /* Software reset */
  73. #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
  74. #define I82559_SELECTIVE_RESET 0x00000002
  75. #define I82559_DUMP 0x00000003
  76. #define I82559_DUMP_WAKEUP 0x00000007
  77. /* 82559 Eeprom interface.
  78. */
  79. #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
  80. #define EE_CS 0x02 /* EEPROM chip select. */
  81. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  82. #define EE_WRITE_0 0x01
  83. #define EE_WRITE_1 0x05
  84. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  85. #define EE_ENB (0x4800 | EE_CS)
  86. #define EE_CMD_BITS 3
  87. #define EE_DATA_BITS 16
  88. /* The EEPROM commands include the alway-set leading bit.
  89. */
  90. #define EE_EWENB_CMD (4 << addr_len)
  91. #define EE_WRITE_CMD (5 << addr_len)
  92. #define EE_READ_CMD (6 << addr_len)
  93. #define EE_ERASE_CMD (7 << addr_len)
  94. /* Receive frame descriptors.
  95. */
  96. struct RxFD {
  97. volatile u16 status;
  98. volatile u16 control;
  99. volatile u32 link; /* struct RxFD * */
  100. volatile u32 rx_buf_addr; /* void * */
  101. volatile u32 count;
  102. volatile u8 data[PKTSIZE_ALIGN];
  103. };
  104. #define RFD_STATUS_C 0x8000 /* completion of received frame */
  105. #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
  106. #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
  107. #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
  108. #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
  109. #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
  110. #define RFD_COUNT_MASK 0x3fff
  111. #define RFD_COUNT_F 0x4000
  112. #define RFD_COUNT_EOF 0x8000
  113. #define RFD_RX_CRC 0x0800 /* crc error */
  114. #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
  115. #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
  116. #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
  117. #define RFD_RX_SHORT 0x0080 /* short frame error */
  118. #define RFD_RX_LENGTH 0x0020
  119. #define RFD_RX_ERROR 0x0010 /* receive error */
  120. #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
  121. #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
  122. #define RFD_RX_TCO 0x0001 /* TCO indication */
  123. /* Transmit frame descriptors
  124. */
  125. struct TxFD { /* Transmit frame descriptor set. */
  126. volatile u16 status;
  127. volatile u16 command;
  128. volatile u32 link; /* void * */
  129. volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
  130. volatile s32 count;
  131. volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
  132. volatile s32 tx_buf_size0; /* Length of Tx frame. */
  133. volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
  134. volatile s32 tx_buf_size1; /* Length of Tx frame. */
  135. };
  136. #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
  137. #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
  138. #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
  139. #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
  140. #define TxCB_CMD_S 0x4000 /* suspend on completion */
  141. #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
  142. #define TxCB_COUNT_MASK 0x3fff
  143. #define TxCB_COUNT_EOF 0x8000
  144. /* The Speedo3 Rx and Tx frame/buffer descriptors.
  145. */
  146. struct descriptor { /* A generic descriptor. */
  147. volatile u16 status;
  148. volatile u16 command;
  149. volatile u32 link; /* struct descriptor * */
  150. unsigned char params[0];
  151. };
  152. #define CONFIG_SYS_CMD_EL 0x8000
  153. #define CONFIG_SYS_CMD_SUSPEND 0x4000
  154. #define CONFIG_SYS_CMD_INT 0x2000
  155. #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
  156. #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
  157. #define CONFIG_SYS_STATUS_C 0x8000
  158. #define CONFIG_SYS_STATUS_OK 0x2000
  159. /* Misc.
  160. */
  161. #define NUM_RX_DESC PKTBUFSRX
  162. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  163. #define TOUT_LOOP 1000000
  164. static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
  165. static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
  166. static int rx_next; /* RX descriptor ring pointer */
  167. static int tx_next; /* TX descriptor ring pointer */
  168. static int tx_threshold;
  169. /*
  170. * The parameters for a CmdConfigure operation.
  171. * There are so many options that it would be difficult to document
  172. * each bit. We mostly use the default or recommended settings.
  173. */
  174. static const char i82558_config_cmd[] = {
  175. 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
  176. 0, 0x2E, 0, 0x60, 0x08, 0x88,
  177. 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
  178. 0x31, 0x05,
  179. };
  180. static void init_rx_ring (struct eth_device *dev);
  181. static void purge_tx_ring (struct eth_device *dev);
  182. static void read_hw_addr (struct eth_device *dev, bd_t * bis);
  183. static int eepro100_init (struct eth_device *dev, bd_t * bis);
  184. static int eepro100_send(struct eth_device *dev, void *packet, int length);
  185. static int eepro100_recv (struct eth_device *dev);
  186. static void eepro100_halt (struct eth_device *dev);
  187. #if defined(CONFIG_E500)
  188. #define bus_to_phys(a) (a)
  189. #define phys_to_bus(a) (a)
  190. #else
  191. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  192. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  193. #endif
  194. static inline int INW (struct eth_device *dev, u_long addr)
  195. {
  196. return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
  197. }
  198. static inline void OUTW (struct eth_device *dev, int command, u_long addr)
  199. {
  200. *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
  201. }
  202. static inline void OUTL (struct eth_device *dev, int command, u_long addr)
  203. {
  204. *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
  205. }
  206. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  207. static inline int INL (struct eth_device *dev, u_long addr)
  208. {
  209. return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
  210. }
  211. static int get_phyreg (struct eth_device *dev, unsigned char addr,
  212. unsigned char reg, unsigned short *value)
  213. {
  214. int cmd;
  215. int timeout = 50;
  216. /* read requested data */
  217. cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  218. OUTL (dev, cmd, SCBCtrlMDI);
  219. do {
  220. udelay(1000);
  221. cmd = INL (dev, SCBCtrlMDI);
  222. } while (!(cmd & (1 << 28)) && (--timeout));
  223. if (timeout == 0)
  224. return -1;
  225. *value = (unsigned short) (cmd & 0xffff);
  226. return 0;
  227. }
  228. static int set_phyreg (struct eth_device *dev, unsigned char addr,
  229. unsigned char reg, unsigned short value)
  230. {
  231. int cmd;
  232. int timeout = 50;
  233. /* write requested data */
  234. cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  235. OUTL (dev, cmd | value, SCBCtrlMDI);
  236. while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
  237. udelay(1000);
  238. if (timeout == 0)
  239. return -1;
  240. return 0;
  241. }
  242. /* Check if given phyaddr is valid, i.e. there is a PHY connected.
  243. * Do this by checking model value field from ID2 register.
  244. */
  245. static struct eth_device* verify_phyaddr (const char *devname,
  246. unsigned char addr)
  247. {
  248. struct eth_device *dev;
  249. unsigned short value;
  250. unsigned char model;
  251. dev = eth_get_dev_by_name(devname);
  252. if (dev == NULL) {
  253. printf("%s: no such device\n", devname);
  254. return NULL;
  255. }
  256. /* read id2 register */
  257. if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
  258. printf("%s: mii read timeout!\n", devname);
  259. return NULL;
  260. }
  261. /* get model */
  262. model = (unsigned char)((value >> 4) & 0x003f);
  263. if (model == 0) {
  264. printf("%s: no PHY at address %d\n", devname, addr);
  265. return NULL;
  266. }
  267. return dev;
  268. }
  269. static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
  270. int reg)
  271. {
  272. unsigned short value = 0;
  273. struct eth_device *dev;
  274. dev = verify_phyaddr(bus->name, addr);
  275. if (dev == NULL)
  276. return -1;
  277. if (get_phyreg(dev, addr, reg, &value) != 0) {
  278. printf("%s: mii read timeout!\n", bus->name);
  279. return -1;
  280. }
  281. return value;
  282. }
  283. static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
  284. int reg, u16 value)
  285. {
  286. struct eth_device *dev;
  287. dev = verify_phyaddr(bus->name, addr);
  288. if (dev == NULL)
  289. return -1;
  290. if (set_phyreg(dev, addr, reg, value) != 0) {
  291. printf("%s: mii write timeout!\n", bus->name);
  292. return -1;
  293. }
  294. return 0;
  295. }
  296. #endif
  297. /* Wait for the chip get the command.
  298. */
  299. static int wait_for_eepro100 (struct eth_device *dev)
  300. {
  301. int i;
  302. for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
  303. if (i >= TOUT_LOOP) {
  304. return 0;
  305. }
  306. }
  307. return 1;
  308. }
  309. static struct pci_device_id supported[] = {
  310. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
  311. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
  312. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
  313. {}
  314. };
  315. int eepro100_initialize (bd_t * bis)
  316. {
  317. pci_dev_t devno;
  318. int card_number = 0;
  319. struct eth_device *dev;
  320. u32 iobase, status;
  321. int idx = 0;
  322. while (1) {
  323. /* Find PCI device
  324. */
  325. if ((devno = pci_find_devices (supported, idx++)) < 0) {
  326. break;
  327. }
  328. pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
  329. iobase &= ~0xf;
  330. #ifdef DEBUG
  331. printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
  332. iobase);
  333. #endif
  334. pci_write_config_dword (devno,
  335. PCI_COMMAND,
  336. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  337. /* Check if I/O accesses and Bus Mastering are enabled.
  338. */
  339. pci_read_config_dword (devno, PCI_COMMAND, &status);
  340. if (!(status & PCI_COMMAND_MEMORY)) {
  341. printf ("Error: Can not enable MEM access.\n");
  342. continue;
  343. }
  344. if (!(status & PCI_COMMAND_MASTER)) {
  345. printf ("Error: Can not enable Bus Mastering.\n");
  346. continue;
  347. }
  348. dev = (struct eth_device *) malloc (sizeof *dev);
  349. if (!dev) {
  350. printf("eepro100: Can not allocate memory\n");
  351. break;
  352. }
  353. memset(dev, 0, sizeof(*dev));
  354. sprintf (dev->name, "i82559#%d", card_number);
  355. dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
  356. dev->iobase = bus_to_phys (iobase);
  357. dev->init = eepro100_init;
  358. dev->halt = eepro100_halt;
  359. dev->send = eepro100_send;
  360. dev->recv = eepro100_recv;
  361. eth_register (dev);
  362. #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
  363. /* register mii command access routines */
  364. int retval;
  365. struct mii_dev *mdiodev = mdio_alloc();
  366. if (!mdiodev)
  367. return -ENOMEM;
  368. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  369. mdiodev->read = eepro100_miiphy_read;
  370. mdiodev->write = eepro100_miiphy_write;
  371. retval = mdio_register(mdiodev);
  372. if (retval < 0)
  373. return retval;
  374. #endif
  375. card_number++;
  376. /* Set the latency timer for value.
  377. */
  378. pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
  379. udelay (10 * 1000);
  380. read_hw_addr (dev, bis);
  381. }
  382. return card_number;
  383. }
  384. static int eepro100_init (struct eth_device *dev, bd_t * bis)
  385. {
  386. int i, status = -1;
  387. int tx_cur;
  388. struct descriptor *ias_cmd, *cfg_cmd;
  389. /* Reset the ethernet controller
  390. */
  391. OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
  392. udelay (20);
  393. OUTL (dev, I82559_RESET, SCBPort);
  394. udelay (20);
  395. if (!wait_for_eepro100 (dev)) {
  396. printf ("Error: Can not reset ethernet controller.\n");
  397. goto Done;
  398. }
  399. OUTL (dev, 0, SCBPointer);
  400. OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
  401. if (!wait_for_eepro100 (dev)) {
  402. printf ("Error: Can not reset ethernet controller.\n");
  403. goto Done;
  404. }
  405. OUTL (dev, 0, SCBPointer);
  406. OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
  407. /* Initialize Rx and Tx rings.
  408. */
  409. init_rx_ring (dev);
  410. purge_tx_ring (dev);
  411. /* Tell the adapter where the RX ring is located.
  412. */
  413. if (!wait_for_eepro100 (dev)) {
  414. printf ("Error: Can not reset ethernet controller.\n");
  415. goto Done;
  416. }
  417. OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
  418. OUTW (dev, SCB_M | RUC_START, SCBCmd);
  419. /* Send the Configure frame */
  420. tx_cur = tx_next;
  421. tx_next = ((tx_next + 1) % NUM_TX_DESC);
  422. cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
  423. cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
  424. cfg_cmd->status = 0;
  425. cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  426. memcpy (cfg_cmd->params, i82558_config_cmd,
  427. sizeof (i82558_config_cmd));
  428. if (!wait_for_eepro100 (dev)) {
  429. printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
  430. goto Done;
  431. }
  432. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  433. OUTW (dev, SCB_M | CU_START, SCBCmd);
  434. for (i = 0;
  435. !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
  436. i++) {
  437. if (i >= TOUT_LOOP) {
  438. printf ("%s: Tx error buffer not ready\n", dev->name);
  439. goto Done;
  440. }
  441. }
  442. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
  443. printf ("TX error status = 0x%08X\n",
  444. le16_to_cpu (tx_ring[tx_cur].status));
  445. goto Done;
  446. }
  447. /* Send the Individual Address Setup frame
  448. */
  449. tx_cur = tx_next;
  450. tx_next = ((tx_next + 1) % NUM_TX_DESC);
  451. ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
  452. ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
  453. ias_cmd->status = 0;
  454. ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  455. memcpy (ias_cmd->params, dev->enetaddr, 6);
  456. /* Tell the adapter where the TX ring is located.
  457. */
  458. if (!wait_for_eepro100 (dev)) {
  459. printf ("Error: Can not reset ethernet controller.\n");
  460. goto Done;
  461. }
  462. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  463. OUTW (dev, SCB_M | CU_START, SCBCmd);
  464. for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
  465. i++) {
  466. if (i >= TOUT_LOOP) {
  467. printf ("%s: Tx error buffer not ready\n",
  468. dev->name);
  469. goto Done;
  470. }
  471. }
  472. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
  473. printf ("TX error status = 0x%08X\n",
  474. le16_to_cpu (tx_ring[tx_cur].status));
  475. goto Done;
  476. }
  477. status = 0;
  478. Done:
  479. return status;
  480. }
  481. static int eepro100_send(struct eth_device *dev, void *packet, int length)
  482. {
  483. int i, status = -1;
  484. int tx_cur;
  485. if (length <= 0) {
  486. printf ("%s: bad packet size: %d\n", dev->name, length);
  487. goto Done;
  488. }
  489. tx_cur = tx_next;
  490. tx_next = (tx_next + 1) % NUM_TX_DESC;
  491. tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
  492. TxCB_CMD_SF |
  493. TxCB_CMD_S |
  494. TxCB_CMD_EL );
  495. tx_ring[tx_cur].status = 0;
  496. tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
  497. tx_ring[tx_cur].link =
  498. cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  499. tx_ring[tx_cur].tx_desc_addr =
  500. cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
  501. tx_ring[tx_cur].tx_buf_addr0 =
  502. cpu_to_le32 (phys_to_bus ((u_long) packet));
  503. tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
  504. if (!wait_for_eepro100 (dev)) {
  505. printf ("%s: Tx error ethernet controller not ready.\n",
  506. dev->name);
  507. goto Done;
  508. }
  509. /* Send the packet.
  510. */
  511. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  512. OUTW (dev, SCB_M | CU_START, SCBCmd);
  513. for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
  514. i++) {
  515. if (i >= TOUT_LOOP) {
  516. printf ("%s: Tx error buffer not ready\n", dev->name);
  517. goto Done;
  518. }
  519. }
  520. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
  521. printf ("TX error status = 0x%08X\n",
  522. le16_to_cpu (tx_ring[tx_cur].status));
  523. goto Done;
  524. }
  525. status = length;
  526. Done:
  527. return status;
  528. }
  529. static int eepro100_recv (struct eth_device *dev)
  530. {
  531. u16 status, stat;
  532. int rx_prev, length = 0;
  533. stat = INW (dev, SCBStatus);
  534. OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
  535. for (;;) {
  536. status = le16_to_cpu (rx_ring[rx_next].status);
  537. if (!(status & RFD_STATUS_C)) {
  538. break;
  539. }
  540. /* Valid frame status.
  541. */
  542. if ((status & RFD_STATUS_OK)) {
  543. /* A valid frame received.
  544. */
  545. length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
  546. /* Pass the packet up to the protocol
  547. * layers.
  548. */
  549. net_process_received_packet((u8 *)rx_ring[rx_next].data,
  550. length);
  551. } else {
  552. /* There was an error.
  553. */
  554. printf ("RX error status = 0x%08X\n", status);
  555. }
  556. rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
  557. rx_ring[rx_next].status = 0;
  558. rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
  559. rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
  560. rx_ring[rx_prev].control = 0;
  561. /* Update entry information.
  562. */
  563. rx_next = (rx_next + 1) % NUM_RX_DESC;
  564. }
  565. if (stat & SCB_STATUS_RNR) {
  566. printf ("%s: Receiver is not ready, restart it !\n", dev->name);
  567. /* Reinitialize Rx ring.
  568. */
  569. init_rx_ring (dev);
  570. if (!wait_for_eepro100 (dev)) {
  571. printf ("Error: Can not restart ethernet controller.\n");
  572. goto Done;
  573. }
  574. OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
  575. OUTW (dev, SCB_M | RUC_START, SCBCmd);
  576. }
  577. Done:
  578. return length;
  579. }
  580. static void eepro100_halt (struct eth_device *dev)
  581. {
  582. /* Reset the ethernet controller
  583. */
  584. OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
  585. udelay (20);
  586. OUTL (dev, I82559_RESET, SCBPort);
  587. udelay (20);
  588. if (!wait_for_eepro100 (dev)) {
  589. printf ("Error: Can not reset ethernet controller.\n");
  590. goto Done;
  591. }
  592. OUTL (dev, 0, SCBPointer);
  593. OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
  594. if (!wait_for_eepro100 (dev)) {
  595. printf ("Error: Can not reset ethernet controller.\n");
  596. goto Done;
  597. }
  598. OUTL (dev, 0, SCBPointer);
  599. OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
  600. Done:
  601. return;
  602. }
  603. /* SROM Read.
  604. */
  605. static int read_eeprom (struct eth_device *dev, int location, int addr_len)
  606. {
  607. unsigned short retval = 0;
  608. int read_cmd = location | EE_READ_CMD;
  609. int i;
  610. OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
  611. OUTW (dev, EE_ENB, SCBeeprom);
  612. /* Shift the read command bits out. */
  613. for (i = 12; i >= 0; i--) {
  614. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  615. OUTW (dev, EE_ENB | dataval, SCBeeprom);
  616. udelay (1);
  617. OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  618. udelay (1);
  619. }
  620. OUTW (dev, EE_ENB, SCBeeprom);
  621. for (i = 15; i >= 0; i--) {
  622. OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
  623. udelay (1);
  624. retval = (retval << 1) |
  625. ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
  626. OUTW (dev, EE_ENB, SCBeeprom);
  627. udelay (1);
  628. }
  629. /* Terminate the EEPROM access. */
  630. OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
  631. return retval;
  632. }
  633. #ifdef CONFIG_EEPRO100_SROM_WRITE
  634. int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
  635. {
  636. unsigned short dataval;
  637. int enable_cmd = 0x3f | EE_EWENB_CMD;
  638. int write_cmd = location | EE_WRITE_CMD;
  639. int i;
  640. unsigned long datalong, tmplong;
  641. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  642. udelay(1);
  643. OUTW(dev, EE_ENB, SCBeeprom);
  644. /* Shift the enable command bits out. */
  645. for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
  646. {
  647. dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  648. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  649. udelay(1);
  650. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  651. udelay(1);
  652. }
  653. OUTW(dev, EE_ENB, SCBeeprom);
  654. udelay(1);
  655. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  656. udelay(1);
  657. OUTW(dev, EE_ENB, SCBeeprom);
  658. /* Shift the write command bits out. */
  659. for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
  660. {
  661. dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  662. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  663. udelay(1);
  664. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  665. udelay(1);
  666. }
  667. /* Write the data */
  668. datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
  669. for (i = 0; i< EE_DATA_BITS; i++)
  670. {
  671. /* Extract and move data bit to bit DI */
  672. dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
  673. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  674. udelay(1);
  675. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  676. udelay(1);
  677. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  678. udelay(1);
  679. datalong = datalong << 1; /* Adjust significant data bit*/
  680. }
  681. /* Finish up command (toggle CS) */
  682. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  683. udelay(1); /* delay for more than 250 ns */
  684. OUTW(dev, EE_ENB, SCBeeprom);
  685. /* Wait for programming ready (D0 = 1) */
  686. tmplong = 10;
  687. do
  688. {
  689. dataval = INW(dev, SCBeeprom);
  690. if (dataval & EE_DATA_READ)
  691. break;
  692. udelay(10000);
  693. }
  694. while (-- tmplong);
  695. if (tmplong == 0)
  696. {
  697. printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
  698. return -1;
  699. }
  700. /* Terminate the EEPROM access. */
  701. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  702. return 0;
  703. }
  704. #endif
  705. static void init_rx_ring (struct eth_device *dev)
  706. {
  707. int i;
  708. for (i = 0; i < NUM_RX_DESC; i++) {
  709. rx_ring[i].status = 0;
  710. rx_ring[i].control =
  711. (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
  712. rx_ring[i].link =
  713. cpu_to_le32 (phys_to_bus
  714. ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
  715. rx_ring[i].rx_buf_addr = 0xffffffff;
  716. rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
  717. }
  718. rx_next = 0;
  719. }
  720. static void purge_tx_ring (struct eth_device *dev)
  721. {
  722. int i;
  723. tx_next = 0;
  724. tx_threshold = 0x01208000;
  725. for (i = 0; i < NUM_TX_DESC; i++) {
  726. tx_ring[i].status = 0;
  727. tx_ring[i].command = 0;
  728. tx_ring[i].link = 0;
  729. tx_ring[i].tx_desc_addr = 0;
  730. tx_ring[i].count = 0;
  731. tx_ring[i].tx_buf_addr0 = 0;
  732. tx_ring[i].tx_buf_size0 = 0;
  733. tx_ring[i].tx_buf_addr1 = 0;
  734. tx_ring[i].tx_buf_size1 = 0;
  735. }
  736. }
  737. static void read_hw_addr (struct eth_device *dev, bd_t * bis)
  738. {
  739. u16 sum = 0;
  740. int i, j;
  741. int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
  742. for (j = 0, i = 0; i < 0x40; i++) {
  743. u16 value = read_eeprom (dev, i, addr_len);
  744. sum += value;
  745. if (i < 3) {
  746. dev->enetaddr[j++] = value;
  747. dev->enetaddr[j++] = value >> 8;
  748. }
  749. }
  750. if (sum != 0xBABA) {
  751. memset (dev->enetaddr, 0, ETH_ALEN);
  752. #ifdef DEBUG
  753. printf ("%s: Invalid EEPROM checksum %#4.4x, "
  754. "check settings before activating this device!\n",
  755. dev->name, sum);
  756. #endif
  757. }
  758. }