MPC8349EMDS.h 21 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * mpc8349emds board configuration file
  25. *
  26. */
  27. #ifndef __CONFIG_H
  28. #define __CONFIG_H
  29. #define DEBUG
  30. #undef DEBUG
  31. /*
  32. * High Level Configuration Options
  33. */
  34. #define CONFIG_E300 1 /* E300 Family */
  35. #define CONFIG_MPC83XX 1 /* MPC83XX family */
  36. #define CONFIG_MPC8349 1 /* MPC8349 specific */
  37. #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
  38. /* FIXME: Real PCI support will come in a follow-up update. */
  39. #undef CONFIG_PCI
  40. #define PCI_66M
  41. #ifdef PCI_66M
  42. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  43. #else
  44. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  45. #endif
  46. #ifndef CONFIG_SYS_CLK_FREQ
  47. #ifdef PCI_66M
  48. #define CONFIG_SYS_CLK_FREQ 66000000
  49. #else
  50. #define CONFIG_SYS_CLK_FREQ 33000000
  51. #endif
  52. #endif
  53. #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  54. #define CFG_IMMRBAR 0xE0000000
  55. #undef CFG_DRAM_TEST /* memory test, takes time */
  56. #define CFG_MEMTEST_START 0x00000000 /* memtest region */
  57. #define CFG_MEMTEST_END 0x00100000
  58. /*
  59. * DDR Setup
  60. */
  61. #define CONFIG_DDR_ECC /* only for ECC DDR module */
  62. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  63. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  64. /*
  65. * 32-bit data path mode.
  66. *
  67. * Please note that using this mode for devices with the real density of 64-bit
  68. * effectively reduces the amount of available memory due to the effect of
  69. * wrapping around while translating address to row/columns, for example in the
  70. * 256MB module the upper 128MB get aliased with contents of the lower
  71. * 128MB); normally this define should be used for devices with real 32-bit
  72. * data path.
  73. */
  74. #undef CONFIG_DDR_32BIT
  75. #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
  76. #define CFG_SDRAM_BASE CFG_DDR_BASE
  77. #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
  78. #undef CONFIG_DDR_2T_TIMING
  79. #if defined(CONFIG_SPD_EEPROM)
  80. /*
  81. * Determine DDR configuration from I2C interface.
  82. */
  83. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  84. #else
  85. /*
  86. * Manually set up DDR parameters
  87. */
  88. #define CFG_DDR_SIZE 256 /* MB */
  89. #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  90. #define CFG_DDR_TIMING_1 0x36332321
  91. #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  92. #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  93. #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  94. #if defined(CONFIG_DDR_32BIT)
  95. /* set burst length to 8 for 32-bit data path */
  96. #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
  97. #else
  98. /* the default burst length is 4 - for 64-bit data path */
  99. #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
  100. #endif
  101. #endif
  102. /*
  103. * SDRAM on the Local Bus
  104. */
  105. #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  106. #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  107. /*
  108. * FLASH on the Local Bus
  109. */
  110. #define CFG_FLASH_CFI /* use the Common Flash Interface */
  111. #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
  112. #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
  113. #define CFG_FLASH_SIZE 8 /* flash size in MB */
  114. /* #define CFG_FLASH_USE_BUFFER_WRITE */
  115. #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
  116. (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
  117. BR_V) /* valid */
  118. #define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
  119. #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
  120. #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
  121. #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
  122. #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
  123. #undef CFG_FLASH_CHECKSUM
  124. #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  125. #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  126. #define CFG_MID_FLASH_JUMP 0x7F000000
  127. #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  128. #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  129. #define CFG_RAMBOOT
  130. #else
  131. #undef CFG_RAMBOOT
  132. #endif
  133. /*
  134. * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  135. */
  136. #define CFG_BCSR 0xF8000000
  137. #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
  138. #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
  139. #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
  140. #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */
  141. #define CONFIG_L1_INIT_RAM
  142. #define CFG_INIT_RAM_LOCK 1
  143. #define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */
  144. #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
  145. #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  146. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  147. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  148. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  149. #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  150. /*
  151. * Local Bus LCRR and LBCR regs
  152. * LCRR: DLL bypass, Clock divider is 4
  153. * External Local Bus rate is
  154. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  155. */
  156. #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
  157. #define CFG_LBC_LBCR 0x00000000
  158. #define CFG_LB_SDRAM /* if board has SRDAM on local bus */
  159. #ifdef CFG_LB_SDRAM
  160. /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
  161. /*
  162. * Base Register 2 and Option Register 2 configure SDRAM.
  163. * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
  164. *
  165. * For BR2, need:
  166. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  167. * port-size = 32-bits = BR2[19:20] = 11
  168. * no parity checking = BR2[21:22] = 00
  169. * SDRAM for MSEL = BR2[24:26] = 011
  170. * Valid = BR[31] = 1
  171. *
  172. * 0 4 8 12 16 20 24 28
  173. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  174. *
  175. * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
  176. * FIXME: the top 17 bits of BR2.
  177. */
  178. #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
  179. #define CFG_LBLAWBAR2_PRELIM 0xF0000000
  180. #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */
  181. /*
  182. * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
  183. *
  184. * For OR2, need:
  185. * 64MB mask for AM, OR2[0:7] = 1111 1100
  186. * XAM, OR2[17:18] = 11
  187. * 9 columns OR2[19-21] = 010
  188. * 13 rows OR2[23-25] = 100
  189. * EAD set for extra time OR[31] = 1
  190. *
  191. * 0 4 8 12 16 20 24 28
  192. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  193. */
  194. #define CFG_OR2_PRELIM 0xFC006901
  195. #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
  196. #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
  197. /*
  198. * LSDMR masks
  199. */
  200. #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
  201. #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
  202. #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
  203. #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
  204. #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
  205. #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
  206. #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
  207. #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
  208. #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
  209. #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
  210. #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
  211. #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
  212. #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
  213. #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
  214. #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
  215. #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
  216. #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
  217. #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
  218. #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
  219. #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
  220. #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
  221. #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
  222. #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
  223. #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
  224. #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
  225. #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
  226. #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
  227. | CFG_LBC_LSDMR_BSMA1516 \
  228. | CFG_LBC_LSDMR_RFCR8 \
  229. | CFG_LBC_LSDMR_PRETOACT6 \
  230. | CFG_LBC_LSDMR_ACTTORW3 \
  231. | CFG_LBC_LSDMR_BL8 \
  232. | CFG_LBC_LSDMR_WRC3 \
  233. | CFG_LBC_LSDMR_CL3 \
  234. )
  235. /*
  236. * SDRAM Controller configuration sequence.
  237. */
  238. #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
  239. | CFG_LBC_LSDMR_OP_PCHALL)
  240. #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
  241. | CFG_LBC_LSDMR_OP_ARFRSH)
  242. #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
  243. | CFG_LBC_LSDMR_OP_ARFRSH)
  244. #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
  245. | CFG_LBC_LSDMR_OP_MRW)
  246. #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
  247. | CFG_LBC_LSDMR_OP_NORMAL)
  248. #endif
  249. /*
  250. * Serial Port
  251. */
  252. #define CONFIG_CONS_INDEX 1
  253. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  254. #define CFG_NS16550
  255. #define CFG_NS16550_SERIAL
  256. #define CFG_NS16550_REG_SIZE 1
  257. #define CFG_NS16550_CLK get_bus_freq(0)
  258. #define CFG_BAUDRATE_TABLE \
  259. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  260. #define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
  261. #define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
  262. /* Use the HUSH parser */
  263. #define CFG_HUSH_PARSER
  264. #ifdef CFG_HUSH_PARSER
  265. #define CFG_PROMPT_HUSH_PS2 "> "
  266. #endif
  267. /* I2C */
  268. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  269. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  270. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  271. #define CFG_I2C_SLAVE 0x7F
  272. #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  273. #define CFG_I2C_OFFSET 0x3000
  274. #define CFG_I2C2_OFFSET 0x3100
  275. /* TSEC */
  276. #define CFG_TSEC1_OFFSET 0x24000
  277. #define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
  278. #define CFG_TSEC2_OFFSET 0x25000
  279. #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
  280. /* IO Configuration */
  281. #define CFG_IO_CONF (\
  282. IO_CONF_UART |\
  283. IO_CONF_TSEC1 |\
  284. IO_CONF_IRQ0 |\
  285. IO_CONF_IRQ1 |\
  286. IO_CONF_IRQ2 |\
  287. IO_CONF_IRQ3 |\
  288. IO_CONF_IRQ4 |\
  289. IO_CONF_IRQ5 |\
  290. IO_CONF_IRQ6 |\
  291. IO_CONF_IRQ7 )
  292. /*
  293. * General PCI
  294. * Addresses are mapped 1-1.
  295. */
  296. #define CFG_PCI1_MEM_BASE 0x80000000
  297. #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  298. #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  299. #define CFG_PCI1_IO_BASE 0x00000000
  300. #define CFG_PCI1_IO_PHYS 0xe2000000
  301. #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  302. #define CFG_PCI2_MEM_BASE 0xA0000000
  303. #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
  304. #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
  305. #define CFG_PCI2_IO_BASE 0x00000000
  306. #define CFG_PCI2_IO_PHYS 0xe3000000
  307. #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
  308. #if defined(CONFIG_PCI)
  309. #define PCI_ALL_PCI1
  310. #if defined(PCI_64BIT)
  311. #undef PCI_ALL_PCI1
  312. #undef PCI_TWO_PCI1
  313. #undef PCI_ONE_PCI1
  314. #endif
  315. #define CONFIG_NET_MULTI
  316. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  317. #undef CONFIG_EEPRO100
  318. #undef CONFIG_TULIP
  319. #if !defined(CONFIG_PCI_PNP)
  320. #define PCI_ENET0_IOADDR 0xFIXME
  321. #define PCI_ENET0_MEMADDR 0xFIXME
  322. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  323. #endif
  324. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  325. #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  326. #endif /* CONFIG_PCI */
  327. /*
  328. * TSEC configuration
  329. */
  330. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  331. #if defined(CONFIG_TSEC_ENET)
  332. #ifndef CONFIG_NET_MULTI
  333. #define CONFIG_NET_MULTI 1
  334. #endif
  335. #define CONFIG_GMII 1 /* MII PHY management */
  336. #define CONFIG_MPC83XX_TSEC1 1
  337. #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
  338. #define CONFIG_MPC83XX_TSEC2 1
  339. #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
  340. #define TSEC1_PHY_ADDR 0
  341. #define TSEC2_PHY_ADDR 1
  342. #define TSEC1_PHYIDX 0
  343. #define TSEC2_PHYIDX 0
  344. /* Options are: TSEC[0-1] */
  345. #define CONFIG_ETHPRIME "TSEC0"
  346. #endif /* CONFIG_TSEC_ENET */
  347. /*
  348. * Configure on-board RTC
  349. */
  350. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  351. #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  352. /*
  353. * Environment
  354. */
  355. #ifndef CFG_RAMBOOT
  356. #define CFG_ENV_IS_IN_FLASH 1
  357. #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
  358. #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  359. #define CFG_ENV_SIZE 0x2000
  360. /* Address and size of Redundant Environment Sector */
  361. #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
  362. #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  363. #else
  364. #define CFG_NO_FLASH 1 /* Flash is not usable now */
  365. #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  366. #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
  367. #define CFG_ENV_SIZE 0x2000
  368. #endif
  369. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  370. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  371. #if defined(CFG_RAMBOOT)
  372. #if defined(CONFIG_PCI)
  373. #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  374. | CFG_CMD_PING \
  375. | CFG_CMD_PCI \
  376. | CFG_CMD_I2C \
  377. | CFG_CMD_DATE) \
  378. & \
  379. ~(CFG_CMD_ENV \
  380. | CFG_CMD_LOADS))
  381. #else
  382. #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  383. | CFG_CMD_PING \
  384. | CFG_CMD_I2C \
  385. | CFG_CMD_DATE) \
  386. & \
  387. ~(CFG_CMD_ENV \
  388. | CFG_CMD_LOADS))
  389. #endif
  390. #else
  391. #if defined(CONFIG_PCI)
  392. #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  393. | CFG_CMD_PCI \
  394. | CFG_CMD_PING \
  395. | CFG_CMD_I2C \
  396. | CFG_CMD_DATE \
  397. )
  398. #else
  399. #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  400. | CFG_CMD_PING \
  401. | CFG_CMD_I2C \
  402. | CFG_CMD_MII \
  403. | CFG_CMD_DATE \
  404. )
  405. #endif
  406. #endif
  407. #include <cmd_confdefs.h>
  408. #undef CONFIG_WATCHDOG /* watchdog disabled */
  409. /*
  410. * Miscellaneous configurable options
  411. */
  412. #define CFG_LONGHELP /* undef to save memory */
  413. #define CFG_LOAD_ADDR 0x2000000 /* default load address */
  414. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  415. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  416. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  417. #else
  418. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  419. #endif
  420. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  421. #define CFG_MAXARGS 16 /* max number of command args */
  422. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  423. #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
  424. /*
  425. * For booting Linux, the board info and command line data
  426. * have to be in the first 8 MB of memory, since this is
  427. * the maximum mapped by the Linux kernel during initialization.
  428. */
  429. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  430. /* Cache Configuration */
  431. #define CFG_DCACHE_SIZE 32768
  432. #define CFG_CACHELINE_SIZE 32
  433. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  434. #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
  435. #endif
  436. #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  437. #if 1 /*528/264*/
  438. #define CFG_HRCW_LOW (\
  439. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  440. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  441. HRCWL_CSB_TO_CLKIN_4X1 |\
  442. HRCWL_VCO_1X2 |\
  443. HRCWL_CORE_TO_CSB_2X1)
  444. #elif 0 /*396/132*/
  445. #define CFG_HRCW_LOW (\
  446. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  447. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  448. HRCWL_CSB_TO_CLKIN_2X1 |\
  449. HRCWL_VCO_1X4 |\
  450. HRCWL_CORE_TO_CSB_3X1)
  451. #elif 0 /*264/132*/
  452. #define CFG_HRCW_LOW (\
  453. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  454. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  455. HRCWL_CSB_TO_CLKIN_2X1 |\
  456. HRCWL_VCO_1X4 |\
  457. HRCWL_CORE_TO_CSB_2X1)
  458. #elif 0 /*132/132*/
  459. #define CFG_HRCW_LOW (\
  460. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  461. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  462. HRCWL_CSB_TO_CLKIN_2X1 |\
  463. HRCWL_VCO_1X4 |\
  464. HRCWL_CORE_TO_CSB_1X1)
  465. #elif 0 /*264/264 */
  466. #define CFG_HRCW_LOW (\
  467. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  468. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  469. HRCWL_CSB_TO_CLKIN_4X1 |\
  470. HRCWL_VCO_1X4 |\
  471. HRCWL_CORE_TO_CSB_1X1)
  472. #endif
  473. #if defined(PCI_64BIT)
  474. #define CFG_HRCW_HIGH (\
  475. HRCWH_PCI_HOST |\
  476. HRCWH_64_BIT_PCI |\
  477. HRCWH_PCI1_ARBITER_ENABLE |\
  478. HRCWH_PCI2_ARBITER_DISABLE |\
  479. HRCWH_CORE_ENABLE |\
  480. HRCWH_FROM_0X00000100 |\
  481. HRCWH_BOOTSEQ_DISABLE |\
  482. HRCWH_SW_WATCHDOG_DISABLE |\
  483. HRCWH_ROM_LOC_LOCAL_16BIT |\
  484. HRCWH_TSEC1M_IN_GMII |\
  485. HRCWH_TSEC2M_IN_GMII )
  486. #else
  487. #define CFG_HRCW_HIGH (\
  488. HRCWH_PCI_HOST |\
  489. HRCWH_32_BIT_PCI |\
  490. HRCWH_PCI1_ARBITER_ENABLE |\
  491. HRCWH_PCI2_ARBITER_ENABLE |\
  492. HRCWH_CORE_ENABLE |\
  493. HRCWH_FROM_0X00000100 |\
  494. HRCWH_BOOTSEQ_DISABLE |\
  495. HRCWH_SW_WATCHDOG_DISABLE |\
  496. HRCWH_ROM_LOC_LOCAL_16BIT |\
  497. HRCWH_TSEC1M_IN_GMII |\
  498. HRCWH_TSEC2M_IN_GMII )
  499. #endif
  500. /* System IO Config */
  501. #define CFG_SICRH SICRH_TSOBI1
  502. #define CFG_SICRL SICRL_LDP_A
  503. #define CFG_HID0_INIT 0x000000000
  504. #define CFG_HID0_FINAL CFG_HID0_INIT
  505. /* #define CFG_HID0_FINAL (\
  506. HID0_ENABLE_INSTRUCTION_CACHE |\
  507. HID0_ENABLE_M_BIT |\
  508. HID0_ENABLE_ADDRESS_BROADCAST ) */
  509. #define CFG_HID2 HID2_HBE
  510. /* DDR @ 0x00000000 */
  511. #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  512. #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  513. /* PCI @ 0x80000000 */
  514. #ifdef CONFIG_PCI
  515. #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  516. #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  517. #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  518. #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  519. #else
  520. #define CFG_IBAT1L (0)
  521. #define CFG_IBAT1U (0)
  522. #define CFG_IBAT2L (0)
  523. #define CFG_IBAT2U (0)
  524. #endif
  525. /* IMMRBAR @ 0xE0000000 */
  526. #define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  527. #define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
  528. /* stack in DCACHE (no backing mem) @ 0xE8000000 */
  529. #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  530. #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  531. /* LBC SDRAM @ 0xF0000000 */
  532. #define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  533. #define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
  534. /* BCSR @ 0xF8000000 */
  535. #define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  536. #define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
  537. /* FLASH @ 0xFE000000 */
  538. #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  539. #define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
  540. #define CFG_DBAT0L CFG_IBAT0L
  541. #define CFG_DBAT0U CFG_IBAT0U
  542. #define CFG_DBAT1L CFG_IBAT1L
  543. #define CFG_DBAT1U CFG_IBAT1U
  544. #define CFG_DBAT2L CFG_IBAT2L
  545. #define CFG_DBAT2U CFG_IBAT2U
  546. #define CFG_DBAT3L CFG_IBAT3L
  547. #define CFG_DBAT3U CFG_IBAT3U
  548. #define CFG_DBAT4L CFG_IBAT4L
  549. #define CFG_DBAT4U CFG_IBAT4U
  550. #define CFG_DBAT5L CFG_IBAT5L
  551. #define CFG_DBAT5U CFG_IBAT5U
  552. #define CFG_DBAT6L CFG_IBAT6L
  553. #define CFG_DBAT6U CFG_IBAT6U
  554. #define CFG_DBAT7L CFG_IBAT7L
  555. #define CFG_DBAT7U CFG_IBAT7U
  556. /*
  557. * Internal Definitions
  558. *
  559. * Boot Flags
  560. */
  561. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  562. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  563. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  564. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  565. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  566. #endif
  567. /*
  568. * Environment Configuration
  569. */
  570. #define CONFIG_ENV_OVERWRITE
  571. #if defined(CONFIG_TSEC_ENET)
  572. #define CONFIG_ETHADDR 00:04:9f:ef:23:33
  573. #define CONFIG_HAS_ETH1
  574. #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
  575. #endif
  576. #define CONFIG_IPADDR 192.168.205.5
  577. #define CONFIG_HOSTNAME mpc8349emds
  578. #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
  579. #define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage
  580. #define CONFIG_SERVERIP 192.168.1.1
  581. #define CONFIG_GATEWAYIP 192.168.1.1
  582. #define CONFIG_NETMASK 255.255.255.0
  583. #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  584. #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  585. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  586. #define CONFIG_BAUDRATE 115200
  587. #define CONFIG_PREBOOT "echo;" \
  588. "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  589. "echo"
  590. #define CONFIG_EXTRA_ENV_SETTINGS \
  591. "netdev=eth0\0" \
  592. "hostname=mpc8349emds\0" \
  593. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  594. "nfsroot=${serverip}:${rootpath}\0" \
  595. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  596. "addip=setenv bootargs ${bootargs} " \
  597. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  598. ":${hostname}:${netdev}:off panic=1\0" \
  599. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  600. "flash_nfs=run nfsargs addip addtty;" \
  601. "bootm ${kernel_addr}\0" \
  602. "flash_self=run ramargs addip addtty;" \
  603. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  604. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  605. "bootm\0" \
  606. "rootpath=/opt/eldk/ppc_6xx\0" \
  607. "bootfile=/tftpboot/mpc8349emds/uImage\0" \
  608. "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
  609. "update=protect off fe000000 fe03ffff; " \
  610. "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \
  611. "upd=run load;run update\0" \
  612. ""
  613. #define CONFIG_BOOTCOMMAND "run flash_self"
  614. #endif /* __CONFIG_H */