spd_sdram.c 13 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Copyright 2004 Freescale Semiconductor.
  6. * (C) Copyright 2003 Motorola Inc.
  7. * Xianghua Xiao (X.Xiao@motorola.com)
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. *
  27. * Change log:
  28. *
  29. * 20050101: Eran Liberty (liberty@freescale.com)
  30. * Initial file creating (porting from 85XX & 8260)
  31. */
  32. #include <common.h>
  33. #include <asm/processor.h>
  34. #include <i2c.h>
  35. #include <spd.h>
  36. #include <asm/mmu.h>
  37. #include <spd_sdram.h>
  38. #ifdef CONFIG_SPD_EEPROM
  39. #if defined(CONFIG_DDR_ECC)
  40. extern void dma_init(void);
  41. extern uint dma_check(void);
  42. extern int dma_xfer(void *dest, uint count, void *src);
  43. #endif
  44. #ifndef CFG_READ_SPD
  45. #define CFG_READ_SPD i2c_read
  46. #endif
  47. /*
  48. * Convert picoseconds into clock cycles (rounding up if needed).
  49. */
  50. int
  51. picos_to_clk(int picos)
  52. {
  53. int clks;
  54. clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
  55. if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
  56. clks++;
  57. }
  58. return clks;
  59. }
  60. unsigned int banksize(unsigned char row_dens)
  61. {
  62. return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  63. }
  64. int read_spd(uint addr)
  65. {
  66. return ((int) addr);
  67. }
  68. #undef SPD_DEBUG
  69. #ifdef SPD_DEBUG
  70. static void spd_debug(spd_eeprom_t *spd)
  71. {
  72. printf ("\nDIMM type: %-18.18s\n", spd->mpart);
  73. printf ("SPD size: %d\n", spd->info_size);
  74. printf ("EEPROM size: %d\n", 1 << spd->chip_size);
  75. printf ("Memory type: %d\n", spd->mem_type);
  76. printf ("Row addr: %d\n", spd->nrow_addr);
  77. printf ("Column addr: %d\n", spd->ncol_addr);
  78. printf ("# of rows: %d\n", spd->nrows);
  79. printf ("Row density: %d\n", spd->row_dens);
  80. printf ("# of banks: %d\n", spd->nbanks);
  81. printf ("Data width: %d\n",
  82. 256 * spd->dataw_msb + spd->dataw_lsb);
  83. printf ("Chip width: %d\n", spd->primw);
  84. printf ("Refresh rate: %02X\n", spd->refresh);
  85. printf ("CAS latencies: %02X\n", spd->cas_lat);
  86. printf ("Write latencies: %02X\n", spd->write_lat);
  87. printf ("tRP: %d\n", spd->trp);
  88. printf ("tRCD: %d\n", spd->trcd);
  89. printf ("\n");
  90. }
  91. #endif /* SPD_DEBUG */
  92. long int spd_sdram()
  93. {
  94. volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
  95. volatile ddr8349_t *ddr = &immap->ddr;
  96. volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
  97. spd_eeprom_t spd;
  98. unsigned tmp, tmp1;
  99. unsigned int memsize;
  100. unsigned int law_size;
  101. unsigned char caslat;
  102. unsigned int trfc, trfc_clk, trfc_low;
  103. CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
  104. #ifdef SPD_DEBUG
  105. spd_debug(&spd);
  106. #endif
  107. if (spd.nrows > 2) {
  108. puts("DDR:Only two chip selects are supported on ADS.\n");
  109. return 0;
  110. }
  111. if (spd.nrow_addr < 12
  112. || spd.nrow_addr > 14
  113. || spd.ncol_addr < 8
  114. || spd.ncol_addr > 11) {
  115. puts("DDR:Row or Col number unsupported.\n");
  116. return 0;
  117. }
  118. ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  119. ddr->cs_config[2] = ( 1 << 31
  120. | (spd.nrow_addr - 12) << 8
  121. | (spd.ncol_addr - 8) );
  122. debug("\n");
  123. debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
  124. debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
  125. if (spd.nrows == 2) {
  126. ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
  127. | ((banksize(spd.row_dens) >> 23) - 1) );
  128. ddr->cs_config[3] = ( 1<<31
  129. | (spd.nrow_addr-12) << 8
  130. | (spd.ncol_addr-8) );
  131. debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
  132. debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
  133. }
  134. if (spd.mem_type != 0x07) {
  135. puts("No DDR module found!\n");
  136. return 0;
  137. }
  138. /*
  139. * Figure out memory size in Megabytes.
  140. */
  141. memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
  142. /*
  143. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
  144. */
  145. law_size = 19 + __ilog2(memsize);
  146. /*
  147. * Set up LAWBAR for all of DDR.
  148. */
  149. ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
  150. ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  151. debug("DDR:bar=0x%08x\n", ecm->bar);
  152. debug("DDR:ar=0x%08x\n", ecm->ar);
  153. /*
  154. * find the largest CAS
  155. */
  156. if(spd.cas_lat & 0x40) {
  157. caslat = 7;
  158. } else if (spd.cas_lat & 0x20) {
  159. caslat = 6;
  160. } else if (spd.cas_lat & 0x10) {
  161. caslat = 5;
  162. } else if (spd.cas_lat & 0x08) {
  163. caslat = 4;
  164. } else if (spd.cas_lat & 0x04) {
  165. caslat = 3;
  166. } else if (spd.cas_lat & 0x02) {
  167. caslat = 2;
  168. } else if (spd.cas_lat & 0x01) {
  169. caslat = 1;
  170. } else {
  171. puts("DDR:no valid CAS Latency information.\n");
  172. return 0;
  173. }
  174. tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  175. + (spd.clk_cycle & 0x0f));
  176. debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
  177. tmp1 = get_bus_freq(0) / 1000000;
  178. if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
  179. /* 90~230 range, treated as DDR 200 */
  180. if (spd.clk_cycle3 == 0xa0)
  181. caslat -= 2;
  182. else if(spd.clk_cycle2 == 0xa0)
  183. caslat--;
  184. } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
  185. /* 230-280 range, treated as DDR 266 */
  186. if (spd.clk_cycle3 == 0x75)
  187. caslat -= 2;
  188. else if (spd.clk_cycle2 == 0x75)
  189. caslat--;
  190. } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
  191. /* 280~350 range, treated as DDR 333 */
  192. if (spd.clk_cycle3 == 0x60)
  193. caslat -= 2;
  194. else if (spd.clk_cycle2 == 0x60)
  195. caslat--;
  196. } else if (tmp1 < 90 || tmp1 >= 350) {
  197. /* DDR rate out-of-range */
  198. puts("DDR:platform frequency is not fit for DDR rate\n");
  199. return 0;
  200. }
  201. /*
  202. * note: caslat must also be programmed into ddr->sdram_mode
  203. * register.
  204. *
  205. * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  206. * use conservative value here.
  207. */
  208. trfc = spd.trfc * 1000; /* up to ps */
  209. trfc_clk = picos_to_clk(trfc);
  210. trfc_low = (trfc_clk - 8) & 0xf;
  211. ddr->timing_cfg_1 =
  212. (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
  213. ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
  214. ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
  215. ((caslat & 0x07) << 16 ) |
  216. (trfc_low << 12 ) |
  217. ( 0x300 ) |
  218. ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
  219. ddr->timing_cfg_2 = 0x00000800;
  220. debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  221. debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  222. /*
  223. * Only DDR I is supported
  224. * DDR I and II have different mode-register-set definition
  225. */
  226. switch(caslat) {
  227. case 2:
  228. tmp = 0x50; /* 1.5 */
  229. break;
  230. case 3:
  231. tmp = 0x20; /* 2.0 */
  232. break;
  233. case 4:
  234. tmp = 0x60; /* 2.5 */
  235. break;
  236. case 5:
  237. tmp = 0x30; /* 3.0 */
  238. break;
  239. default:
  240. puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
  241. return 0;
  242. }
  243. #if defined (CONFIG_DDR_32BIT)
  244. /* set burst length to 8 for 32-bit data path */
  245. tmp |= 0x03;
  246. #else
  247. /* set burst length to 4 - default for 64-bit data path */
  248. tmp |= 0x02;
  249. #endif
  250. ddr->sdram_mode = tmp;
  251. debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
  252. switch(spd.refresh) {
  253. case 0x00:
  254. case 0x80:
  255. tmp = picos_to_clk(15625000);
  256. break;
  257. case 0x01:
  258. case 0x81:
  259. tmp = picos_to_clk(3900000);
  260. break;
  261. case 0x02:
  262. case 0x82:
  263. tmp = picos_to_clk(7800000);
  264. break;
  265. case 0x03:
  266. case 0x83:
  267. tmp = picos_to_clk(31300000);
  268. break;
  269. case 0x04:
  270. case 0x84:
  271. tmp = picos_to_clk(62500000);
  272. break;
  273. case 0x05:
  274. case 0x85:
  275. tmp = picos_to_clk(125000000);
  276. break;
  277. default:
  278. tmp = 0x512;
  279. break;
  280. }
  281. /*
  282. * Set BSTOPRE to 0x100 for page mode
  283. * If auto-charge is used, set BSTOPRE = 0
  284. */
  285. ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
  286. debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
  287. /*
  288. * Is this an ECC DDR chip?
  289. */
  290. #if defined(CONFIG_DDR_ECC)
  291. if (spd.config == 0x02) {
  292. /* disable error detection */
  293. ddr->err_disable = ~ECC_ERROR_ENABLE;
  294. /* set single bit error threshold to maximum value,
  295. * reset counter to zero */
  296. ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
  297. (0 << ECC_ERROR_MAN_SBEC_SHIFT);
  298. }
  299. debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  300. debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
  301. #endif
  302. asm("sync;isync");
  303. udelay(500);
  304. /*
  305. * SS_EN=1,
  306. * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
  307. * clock cycle after address/command
  308. */
  309. /*ddr->sdram_clk_cntl = 0x82000000;*/
  310. ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
  311. /*
  312. * Figure out the settings for the sdram_cfg register. Build up
  313. * the entire register in 'tmp' before writing since the write into
  314. * the register will actually enable the memory controller, and all
  315. * settings must be done before enabling.
  316. *
  317. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  318. * sdram_cfg[1] = 1 (self-refresh-enable)
  319. * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
  320. */
  321. tmp = 0xc2000000;
  322. #if defined (CONFIG_DDR_32BIT)
  323. /* in 32-Bit mode burst len is 8 beats */
  324. tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
  325. #endif
  326. /*
  327. * sdram_cfg[3] = RD_EN - registered DIMM enable
  328. * A value of 0x26 indicates micron registered DIMMS (micron.com)
  329. */
  330. if (spd.mod_attr == 0x26) {
  331. tmp |= 0x10000000;
  332. }
  333. #if defined(CONFIG_DDR_ECC)
  334. /*
  335. * If the user wanted ECC (enabled via sdram_cfg[2])
  336. */
  337. if (spd.config == 0x02) {
  338. tmp |= SDRAM_CFG_ECC_EN;
  339. }
  340. #endif
  341. #if defined(CONFIG_DDR_2T_TIMING)
  342. /*
  343. * Enable 2T timing by setting sdram_cfg[16].
  344. */
  345. tmp |= SDRAM_CFG_2T_EN;
  346. #endif
  347. ddr->sdram_cfg = tmp;
  348. asm("sync;isync");
  349. udelay(500);
  350. debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
  351. return memsize; /*in MBytes*/
  352. }
  353. #endif /* CONFIG_SPD_EEPROM */
  354. #if defined(CONFIG_DDR_ECC)
  355. /*
  356. * Use timebase counter, get_timer() is not availabe
  357. * at this point of initialization yet.
  358. */
  359. static __inline__ unsigned long get_tbms (void)
  360. {
  361. unsigned long tbl;
  362. unsigned long tbu1, tbu2;
  363. unsigned long ms;
  364. unsigned long long tmp;
  365. ulong tbclk = get_tbclk();
  366. /* get the timebase ticks */
  367. do {
  368. asm volatile ("mftbu %0":"=r" (tbu1):);
  369. asm volatile ("mftb %0":"=r" (tbl):);
  370. asm volatile ("mftbu %0":"=r" (tbu2):);
  371. } while (tbu1 != tbu2);
  372. /* convert ticks to ms */
  373. tmp = (unsigned long long)(tbu1);
  374. tmp = (tmp << 32);
  375. tmp += (unsigned long long)(tbl);
  376. ms = tmp/(tbclk/1000);
  377. return ms;
  378. }
  379. /*
  380. * Initialize all of memory for ECC, then enable errors.
  381. */
  382. //#define CONFIG_DDR_ECC_INIT_VIA_DMA
  383. void ddr_enable_ecc(unsigned int dram_size)
  384. {
  385. uint *p;
  386. volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
  387. volatile ddr8349_t *ddr = &immap->ddr;
  388. unsigned long t_start, t_end;
  389. #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  390. uint i;
  391. #endif
  392. debug("Initialize a Cachline in DRAM\n");
  393. icache_enable();
  394. #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  395. /* Initialise DMA for direct Transfers */
  396. dma_init();
  397. #endif
  398. t_start = get_tbms();
  399. #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  400. debug("DDR init: Cache flush method\n");
  401. for (p = 0; p < (uint *)(dram_size); p++) {
  402. if (((unsigned int)p & 0x1f) == 0) {
  403. ppcDcbz((unsigned long) p);
  404. }
  405. /* write pattern to cache and flush */
  406. *p = (unsigned int)0xdeadbeef;
  407. if (((unsigned int)p & 0x1c) == 0x1c) {
  408. ppcDcbf((unsigned long) p);
  409. }
  410. }
  411. #else
  412. printf("DDR init: DMA method\n");
  413. for (p = 0; p < (uint *)(8 * 1024); p++) {
  414. /* zero one data cache line */
  415. if (((unsigned int)p & 0x1f) == 0) {
  416. ppcDcbz((unsigned long)p);
  417. }
  418. /* write pattern to it and flush */
  419. *p = (unsigned int)0xdeadbeef;
  420. if (((unsigned int)p & 0x1c) == 0x1c) {
  421. ppcDcbf((unsigned long)p);
  422. }
  423. }
  424. /* 8K */
  425. dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
  426. /* 16K */
  427. dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
  428. /* 32K */
  429. dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
  430. /* 64K */
  431. dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
  432. /* 128k */
  433. dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
  434. /* 256k */
  435. dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
  436. /* 512k */
  437. dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
  438. /* 1M */
  439. dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
  440. /* 2M */
  441. dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
  442. /* 4M */
  443. dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
  444. for (i = 1; i < dram_size / 0x800000; i++) {
  445. dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
  446. }
  447. #endif
  448. t_end = get_tbms();
  449. icache_disable();
  450. debug("\nREADY!!\n");
  451. debug("ddr init duration: %ld ms\n", t_end - t_start);
  452. /* Clear All ECC Errors */
  453. if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
  454. ddr->err_detect |= ECC_ERROR_DETECT_MME;
  455. if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
  456. ddr->err_detect |= ECC_ERROR_DETECT_MBE;
  457. if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
  458. ddr->err_detect |= ECC_ERROR_DETECT_SBE;
  459. if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
  460. ddr->err_detect |= ECC_ERROR_DETECT_MSE;
  461. /* Disable ECC-Interrupts */
  462. ddr->err_int_en &= ECC_ERR_INT_DISABLE;
  463. /* Enable errors for ECC */
  464. ddr->err_disable &= ECC_ERROR_ENABLE;
  465. __asm__ __volatile__ ("sync");
  466. __asm__ __volatile__ ("isync");
  467. }
  468. #endif /* CONFIG_DDR_ECC */