mpc8349emds.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602
  1. /*
  2. * (C) Copyright 2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h>
  25. #include <ioports.h>
  26. #include <mpc83xx.h>
  27. #include <asm/mpc8349_pci.h>
  28. #include <i2c.h>
  29. #include <spd.h>
  30. #include <miiphy.h>
  31. #include <command.h>
  32. #if defined(CONFIG_PCI)
  33. #include <pci.h>
  34. #endif
  35. #if defined(CONFIG_SPD_EEPROM)
  36. #include <spd_sdram.h>
  37. #endif
  38. int fixed_sdram(void);
  39. void sdram_init(void);
  40. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
  41. void ddr_enable_ecc(unsigned int dram_size);
  42. #endif
  43. int board_early_init_f (void)
  44. {
  45. volatile u8* bcsr = (volatile u8*)CFG_BCSR;
  46. /* Enable flash write */
  47. bcsr[1] &= ~0x01;
  48. return 0;
  49. }
  50. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  51. long int initdram (int board_type)
  52. {
  53. volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  54. u32 msize = 0;
  55. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  56. return -1;
  57. puts("Initializing\n");
  58. /* DDR SDRAM - Main SODIMM */
  59. im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
  60. #if defined(CONFIG_SPD_EEPROM)
  61. msize = spd_sdram();
  62. #else
  63. msize = fixed_sdram();
  64. #endif
  65. /*
  66. * Initialize SDRAM if it is on local bus.
  67. */
  68. sdram_init();
  69. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  70. /*
  71. * Initialize and enable DDR ECC.
  72. */
  73. ddr_enable_ecc(msize * 1024 * 1024);
  74. #endif
  75. puts(" DDR RAM: ");
  76. /* return total bus SDRAM size(bytes) -- DDR */
  77. return (msize * 1024 * 1024);
  78. }
  79. #if !defined(CONFIG_SPD_EEPROM)
  80. /*************************************************************************
  81. * fixed sdram init -- doesn't use serial presence detect.
  82. ************************************************************************/
  83. int fixed_sdram(void)
  84. {
  85. volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  86. u32 msize = 0;
  87. u32 ddr_size;
  88. u32 ddr_size_log2;
  89. msize = CFG_DDR_SIZE;
  90. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  91. (ddr_size > 1);
  92. ddr_size = ddr_size>>1, ddr_size_log2++) {
  93. if (ddr_size & 1) {
  94. return -1;
  95. }
  96. }
  97. im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
  98. im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  99. #if (CFG_DDR_SIZE != 256)
  100. #warning Currenly any ddr size other than 256 is not supported
  101. #endif
  102. im->ddr.csbnds[2].csbnds = 0x0000000f;
  103. im->ddr.cs_config[2] = CFG_DDR_CONFIG;
  104. /* currently we use only one CS, so disable the other banks */
  105. im->ddr.cs_config[0] = 0;
  106. im->ddr.cs_config[1] = 0;
  107. im->ddr.cs_config[3] = 0;
  108. im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
  109. im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
  110. im->ddr.sdram_cfg =
  111. SDRAM_CFG_SREN
  112. #if defined(CONFIG_DDR_2T_TIMING)
  113. | SDRAM_CFG_2T_EN
  114. #endif
  115. | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
  116. #if defined (CONFIG_DDR_32BIT)
  117. /* for 32-bit mode burst length is 8 */
  118. im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
  119. #endif
  120. im->ddr.sdram_mode = CFG_DDR_MODE;
  121. im->ddr.sdram_interval = CFG_DDR_INTERVAL;
  122. udelay(200);
  123. /* enable DDR controller */
  124. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  125. return msize;
  126. }
  127. #endif/*!CFG_SPD_EEPROM*/
  128. int checkboard (void)
  129. {
  130. puts("Board: Freescale MPC8349EMDS\n");
  131. return 0;
  132. }
  133. #if defined(CONFIG_PCI)
  134. /*
  135. * Initialize PCI Devices, report devices found
  136. */
  137. #ifndef CONFIG_PCI_PNP
  138. static struct pci_config_table pci_mpc8349emds_config_table[] = {
  139. {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
  140. pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  141. PCI_ENET0_MEMADDR,
  142. PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
  143. } },
  144. {}
  145. }
  146. #endif
  147. volatile static struct pci_controller hose[] = {
  148. {
  149. #ifndef CONFIG_PCI_PNP
  150. config_table:pci_mpc8349emds_config_table,
  151. #endif
  152. },
  153. {
  154. #ifndef CONFIG_PCI_PNP
  155. config_table:pci_mpc8349emds_config_table,
  156. #endif
  157. }
  158. };
  159. #endif /* CONFIG_PCI */
  160. void pci_init_board(void)
  161. {
  162. #ifdef CONFIG_PCI
  163. extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
  164. pci_mpc83xx_init(hose);
  165. #endif /* CONFIG_PCI */
  166. }
  167. /*
  168. * if MPC8349EMDS is soldered with SDRAM
  169. */
  170. #if defined(CFG_BR2_PRELIM) \
  171. && defined(CFG_OR2_PRELIM) \
  172. && defined(CFG_LBLAWBAR2_PRELIM) \
  173. && defined(CFG_LBLAWAR2_PRELIM)
  174. /*
  175. * Initialize SDRAM memory on the Local Bus.
  176. */
  177. void sdram_init(void)
  178. {
  179. volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
  180. volatile lbus8349_t *lbc= &immap->lbus;
  181. uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
  182. puts("\n SDRAM on Local Bus: ");
  183. print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  184. /*
  185. * Setup SDRAM Base and Option Registers, already done in cpu_init.c
  186. */
  187. /* setup mtrpt, lsrt and lbcr for LB bus */
  188. lbc->lbcr = CFG_LBC_LBCR;
  189. lbc->mrtpr = CFG_LBC_MRTPR;
  190. lbc->lsrt = CFG_LBC_LSRT;
  191. asm("sync");
  192. /*
  193. * Configure the SDRAM controller Machine Mode Register.
  194. */
  195. lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
  196. lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
  197. asm("sync");
  198. *sdram_addr = 0xff;
  199. udelay(100);
  200. lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
  201. asm("sync");
  202. /*1 times*/
  203. *sdram_addr = 0xff;
  204. udelay(100);
  205. /*2 times*/
  206. *sdram_addr = 0xff;
  207. udelay(100);
  208. /*3 times*/
  209. *sdram_addr = 0xff;
  210. udelay(100);
  211. /*4 times*/
  212. *sdram_addr = 0xff;
  213. udelay(100);
  214. /*5 times*/
  215. *sdram_addr = 0xff;
  216. udelay(100);
  217. /*6 times*/
  218. *sdram_addr = 0xff;
  219. udelay(100);
  220. /*7 times*/
  221. *sdram_addr = 0xff;
  222. udelay(100);
  223. /*8 times*/
  224. *sdram_addr = 0xff;
  225. udelay(100);
  226. /* 0x58636733; mode register write operation */
  227. lbc->lsdmr = CFG_LBC_LSDMR_4;
  228. asm("sync");
  229. *sdram_addr = 0xff;
  230. udelay(100);
  231. lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
  232. asm("sync");
  233. *sdram_addr = 0xff;
  234. udelay(100);
  235. }
  236. #else
  237. void sdram_init(void)
  238. {
  239. put("SDRAM on Local Bus is NOT available!\n");
  240. }
  241. #endif
  242. #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
  243. /*
  244. * ECC user commands
  245. */
  246. void ecc_print_status(void)
  247. {
  248. volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
  249. volatile ddr8349_t *ddr = &immap->ddr;
  250. printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
  251. /* Interrupts */
  252. printf("Memory Error Interrupt Enable:\n");
  253. printf(" Multiple-Bit Error Interrupt Enable: %d\n",
  254. (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
  255. printf(" Single-Bit Error Interrupt Enable: %d\n",
  256. (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
  257. printf(" Memory Select Error Interrupt Enable: %d\n\n",
  258. (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
  259. /* Error disable */
  260. printf("Memory Error Disable:\n");
  261. printf(" Multiple-Bit Error Disable: %d\n",
  262. (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
  263. printf(" Sinle-Bit Error Disable: %d\n",
  264. (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
  265. printf(" Memory Select Error Disable: %d\n\n",
  266. (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
  267. /* Error injection */
  268. printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
  269. ddr->data_err_inject_hi, ddr->data_err_inject_lo);
  270. printf("Memory Data Path Error Injection Mask ECC:\n");
  271. printf(" ECC Mirror Byte: %d\n",
  272. (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
  273. printf(" ECC Injection Enable: %d\n",
  274. (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
  275. printf(" ECC Error Injection Mask: 0x%02x\n\n",
  276. ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
  277. /* SBE counter/threshold */
  278. printf("Memory Single-Bit Error Management (0..255):\n");
  279. printf(" Single-Bit Error Threshold: %d\n",
  280. (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
  281. printf(" Single-Bit Error Counter: %d\n\n",
  282. (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
  283. /* Error detect */
  284. printf("Memory Error Detect:\n");
  285. printf(" Multiple Memory Errors: %d\n",
  286. (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
  287. printf(" Multiple-Bit Error: %d\n",
  288. (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
  289. printf(" Single-Bit Error: %d\n",
  290. (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
  291. printf(" Memory Select Error: %d\n\n",
  292. (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
  293. /* Capture data */
  294. printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
  295. printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
  296. ddr->capture_data_hi, ddr->capture_data_lo);
  297. printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
  298. ddr->capture_ecc & CAPTURE_ECC_ECE);
  299. printf("Memory Error Attributes Capture:\n");
  300. printf(" Data Beat Number: %d\n",
  301. (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
  302. printf(" Transaction Size: %d\n",
  303. (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
  304. printf(" Transaction Source: %d\n",
  305. (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
  306. printf(" Transaction Type: %d\n",
  307. (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
  308. printf(" Error Information Valid: %d\n\n",
  309. ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
  310. }
  311. int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  312. {
  313. volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
  314. volatile ddr8349_t *ddr = &immap->ddr;
  315. volatile u32 val;
  316. u64 *addr, count, val64;
  317. register u64 *i;
  318. if (argc > 4) {
  319. printf ("Usage:\n%s\n", cmdtp->usage);
  320. return 1;
  321. }
  322. if (argc == 2) {
  323. if (strcmp(argv[1], "status") == 0) {
  324. ecc_print_status();
  325. return 0;
  326. } else if (strcmp(argv[1], "captureclear") == 0) {
  327. ddr->capture_address = 0;
  328. ddr->capture_data_hi = 0;
  329. ddr->capture_data_lo = 0;
  330. ddr->capture_ecc = 0;
  331. ddr->capture_attributes = 0;
  332. return 0;
  333. }
  334. }
  335. if (argc == 3) {
  336. if (strcmp(argv[1], "sbecnt") == 0) {
  337. val = simple_strtoul(argv[2], NULL, 10);
  338. if (val > 255) {
  339. printf("Incorrect Counter value, should be 0..255\n");
  340. return 1;
  341. }
  342. val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
  343. val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
  344. ddr->err_sbe = val;
  345. return 0;
  346. } else if (strcmp(argv[1], "sbethr") == 0) {
  347. val = simple_strtoul(argv[2], NULL, 10);
  348. if (val > 255) {
  349. printf("Incorrect Counter value, should be 0..255\n");
  350. return 1;
  351. }
  352. val = (val << ECC_ERROR_MAN_SBET_SHIFT);
  353. val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
  354. ddr->err_sbe = val;
  355. return 0;
  356. } else if (strcmp(argv[1], "errdisable") == 0) {
  357. val = ddr->err_disable;
  358. if (strcmp(argv[2], "+sbe") == 0) {
  359. val |= ECC_ERROR_DISABLE_SBED;
  360. } else if (strcmp(argv[2], "+mbe") == 0) {
  361. val |= ECC_ERROR_DISABLE_MBED;
  362. } else if (strcmp(argv[2], "+mse") == 0) {
  363. val |= ECC_ERROR_DISABLE_MSED;
  364. } else if (strcmp(argv[2], "+all") == 0) {
  365. val |= (ECC_ERROR_DISABLE_SBED |
  366. ECC_ERROR_DISABLE_MBED |
  367. ECC_ERROR_DISABLE_MSED);
  368. } else if (strcmp(argv[2], "-sbe") == 0) {
  369. val &= ~ECC_ERROR_DISABLE_SBED;
  370. } else if (strcmp(argv[2], "-mbe") == 0) {
  371. val &= ~ECC_ERROR_DISABLE_MBED;
  372. } else if (strcmp(argv[2], "-mse") == 0) {
  373. val &= ~ECC_ERROR_DISABLE_MSED;
  374. } else if (strcmp(argv[2], "-all") == 0) {
  375. val &= ~(ECC_ERROR_DISABLE_SBED |
  376. ECC_ERROR_DISABLE_MBED |
  377. ECC_ERROR_DISABLE_MSED);
  378. } else {
  379. printf("Incorrect err_disable field\n");
  380. return 1;
  381. }
  382. ddr->err_disable = val;
  383. __asm__ __volatile__ ("sync");
  384. __asm__ __volatile__ ("isync");
  385. return 0;
  386. } else if (strcmp(argv[1], "errdetectclr") == 0) {
  387. val = ddr->err_detect;
  388. if (strcmp(argv[2], "mme") == 0) {
  389. val |= ECC_ERROR_DETECT_MME;
  390. } else if (strcmp(argv[2], "sbe") == 0) {
  391. val |= ECC_ERROR_DETECT_SBE;
  392. } else if (strcmp(argv[2], "mbe") == 0) {
  393. val |= ECC_ERROR_DETECT_MBE;
  394. } else if (strcmp(argv[2], "mse") == 0) {
  395. val |= ECC_ERROR_DETECT_MSE;
  396. } else if (strcmp(argv[2], "all") == 0) {
  397. val |= (ECC_ERROR_DETECT_MME |
  398. ECC_ERROR_DETECT_MBE |
  399. ECC_ERROR_DETECT_SBE |
  400. ECC_ERROR_DETECT_MSE);
  401. } else {
  402. printf("Incorrect err_detect field\n");
  403. return 1;
  404. }
  405. ddr->err_detect = val;
  406. return 0;
  407. } else if (strcmp(argv[1], "injectdatahi") == 0) {
  408. val = simple_strtoul(argv[2], NULL, 16);
  409. ddr->data_err_inject_hi = val;
  410. return 0;
  411. } else if (strcmp(argv[1], "injectdatalo") == 0) {
  412. val = simple_strtoul(argv[2], NULL, 16);
  413. ddr->data_err_inject_lo = val;
  414. return 0;
  415. } else if (strcmp(argv[1], "injectecc") == 0) {
  416. val = simple_strtoul(argv[2], NULL, 16);
  417. if (val > 0xff) {
  418. printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
  419. return 1;
  420. }
  421. val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
  422. ddr->ecc_err_inject = val;
  423. return 0;
  424. } else if (strcmp(argv[1], "inject") == 0) {
  425. val = ddr->ecc_err_inject;
  426. if (strcmp(argv[2], "en") == 0)
  427. val |= ECC_ERR_INJECT_EIEN;
  428. else if (strcmp(argv[2], "dis") == 0)
  429. val &= ~ECC_ERR_INJECT_EIEN;
  430. else
  431. printf("Incorrect command\n");
  432. ddr->ecc_err_inject = val;
  433. __asm__ __volatile__ ("sync");
  434. __asm__ __volatile__ ("isync");
  435. return 0;
  436. } else if (strcmp(argv[1], "mirror") == 0) {
  437. val = ddr->ecc_err_inject;
  438. if (strcmp(argv[2], "en") == 0)
  439. val |= ECC_ERR_INJECT_EMB;
  440. else if (strcmp(argv[2], "dis") == 0)
  441. val &= ~ECC_ERR_INJECT_EMB;
  442. else
  443. printf("Incorrect command\n");
  444. ddr->ecc_err_inject = val;
  445. return 0;
  446. }
  447. }
  448. if (argc == 4) {
  449. if (strcmp(argv[1], "test") == 0) {
  450. addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
  451. count = simple_strtoul(argv[3], NULL, 16);
  452. if ((u32)addr % 8) {
  453. printf("Address not alligned on double word boundary\n");
  454. return 1;
  455. }
  456. disable_interrupts();
  457. icache_disable();
  458. for (i = addr; i < addr + count; i++) {
  459. /* enable injects */
  460. ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
  461. __asm__ __volatile__ ("sync");
  462. __asm__ __volatile__ ("isync");
  463. /* write memory location injecting errors */
  464. *i = 0x1122334455667788ULL;
  465. __asm__ __volatile__ ("sync");
  466. /* disable injects */
  467. ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
  468. __asm__ __volatile__ ("sync");
  469. __asm__ __volatile__ ("isync");
  470. /* read data, this generates ECC error */
  471. val64 = *i;
  472. __asm__ __volatile__ ("sync");
  473. /* disable errors for ECC */
  474. ddr->err_disable |= ~ECC_ERROR_ENABLE;
  475. __asm__ __volatile__ ("sync");
  476. __asm__ __volatile__ ("isync");
  477. /* re-initialize memory, write the location again
  478. * NOT injecting errors this time */
  479. *i = 0xcafecafecafecafeULL;
  480. __asm__ __volatile__ ("sync");
  481. /* enable errors for ECC */
  482. ddr->err_disable &= ECC_ERROR_ENABLE;
  483. __asm__ __volatile__ ("sync");
  484. __asm__ __volatile__ ("isync");
  485. }
  486. icache_enable();
  487. enable_interrupts();
  488. return 0;
  489. }
  490. }
  491. printf ("Usage:\n%s\n", cmdtp->usage);
  492. return 1;
  493. }
  494. U_BOOT_CMD(
  495. ecc, 4, 0, do_ecc,
  496. "ecc - support for DDR ECC features\n",
  497. "status - print out status info\n"
  498. "ecc captureclear - clear capture regs data\n"
  499. "ecc sbecnt <val> - set Single-Bit Error counter\n"
  500. "ecc sbethr <val> - set Single-Bit Threshold\n"
  501. "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
  502. " [-|+]sbe - Single-Bit Error\n"
  503. " [-|+]mbe - Multiple-Bit Error\n"
  504. " [-|+]mse - Memory Select Error\n"
  505. " [-|+]all - all errors\n"
  506. "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
  507. " mme - Multiple Memory Errors\n"
  508. " sbe - Single-Bit Error\n"
  509. " mbe - Multiple-Bit Error\n"
  510. " mse - Memory Select Error\n"
  511. " all - all errors\n"
  512. "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
  513. "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
  514. "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
  515. "ecc inject <en|dis> - enable/disable error injection\n"
  516. "ecc mirror <en|dis> - enable/disable mirror byte\n"
  517. "ecc test <addr> <cnt> - test mem region:\n"
  518. " - enables injects\n"
  519. " - writes pattern injecting errors\n"
  520. " - disables injects\n"
  521. " - reads pattern back, generates error\n"
  522. " - re-inits memory"
  523. );
  524. #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */