sdram_agilex.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <div64.h>
  10. #include <fdtdec.h>
  11. #include <hang.h>
  12. #include <ram.h>
  13. #include <reset.h>
  14. #include "sdram_soc64.h"
  15. #include <wait_bit.h>
  16. #include <asm/arch/firewall.h>
  17. #include <asm/arch/reset_manager.h>
  18. #include <asm/arch/system_manager.h>
  19. #include <asm/io.h>
  20. #include <linux/sizes.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int sdram_mmr_init_full(struct udevice *dev)
  23. {
  24. struct altera_sdram_platdata *plat = dev->platdata;
  25. struct altera_sdram_priv *priv = dev_get_priv(dev);
  26. u32 i;
  27. int ret;
  28. phys_size_t hw_size;
  29. bd_t bd = {0};
  30. /* Ensure HMC clock is running */
  31. if (poll_hmc_clock_status()) {
  32. debug("DDR: Error as HMC clock was not running\n");
  33. return -EPERM;
  34. }
  35. /* Trying 3 times to do a calibration */
  36. for (i = 0; i < 3; i++) {
  37. ret = wait_for_bit_le32((const void *)(plat->hmc +
  38. DDRCALSTAT),
  39. DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
  40. false);
  41. if (!ret)
  42. break;
  43. emif_reset(plat);
  44. }
  45. if (ret) {
  46. puts("DDR: Error as SDRAM calibration failed\n");
  47. return -EPERM;
  48. }
  49. debug("DDR: Calibration success\n");
  50. /*
  51. * Configure the DDR IO size
  52. * niosreserve0: Used to indicate DDR width &
  53. * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
  54. * bit[8] = 1 if user-mode OCT is present
  55. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  56. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  57. * niosreserve1: IP ADCDS version encoded as 16 bit value
  58. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  59. * 3=EAP, 4-6 are reserved)
  60. * bit[5:3] = Service Pack # (e.g. 1)
  61. * bit[9:6] = Minor Release #
  62. * bit[14:10] = Major Release #
  63. */
  64. /* Configure DDR IO size x16, x32 and x64 mode */
  65. u32 update_value;
  66. update_value = hmc_readl(plat, NIOSRESERVED0);
  67. update_value = (update_value & 0xFF) >> 5;
  68. /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
  69. update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
  70. hmc_ecc_writel(plat, update_value, DDRIOCTRL);
  71. /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
  72. hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
  73. /* assigning the SDRAM size */
  74. phys_size_t size = sdram_calculate_size(plat);
  75. if (size <= 0)
  76. hw_size = PHYS_SDRAM_1_SIZE;
  77. else
  78. hw_size = size;
  79. /* Get bank configuration from devicetree */
  80. ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
  81. (phys_size_t *)&gd->ram_size, &bd);
  82. if (ret) {
  83. puts("DDR: Failed to decode memory node\n");
  84. return -ENXIO;
  85. }
  86. if (gd->ram_size != hw_size) {
  87. printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
  88. gd->ram_size >> 20);
  89. printf(" mismatch with hardware (%lld MiB).\n",
  90. hw_size >> 20);
  91. }
  92. if (gd->ram_size > hw_size) {
  93. printf("DDR: Error: DRAM size from device tree is greater\n");
  94. printf(" than hardware size.\n");
  95. hang();
  96. }
  97. printf("DDR: %lld MiB\n", gd->ram_size >> 20);
  98. /* This enables nonsecure access to DDR */
  99. /* mpuregion0addr_limit */
  100. FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
  101. FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
  102. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
  103. /* nonmpuregion0addr_limit */
  104. FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
  105. FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
  106. /* Enable mpuregion0enable and nonmpuregion0enable */
  107. FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
  108. FW_MPU_DDR_SCR_EN_SET);
  109. u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
  110. /* Enable or disable the DDR ECC */
  111. if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
  112. setbits_le32(plat->hmc + ECCCTRL1,
  113. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  114. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  115. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  116. clrbits_le32(plat->hmc + ECCCTRL1,
  117. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  118. DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
  119. setbits_le32(plat->hmc + ECCCTRL2,
  120. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  121. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  122. setbits_le32(plat->hmc + ERRINTEN,
  123. DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
  124. if (!cpu_has_been_warmreset())
  125. sdram_init_ecc_bits(&bd);
  126. } else {
  127. clrbits_le32(plat->hmc + ECCCTRL1,
  128. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  129. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  130. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  131. clrbits_le32(plat->hmc + ECCCTRL2,
  132. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  133. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  134. }
  135. /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
  136. writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
  137. sdram_size_check(&bd);
  138. priv->info.base = bd.bi_dram[0].start;
  139. priv->info.size = gd->ram_size;
  140. debug("DDR: HMC init success\n");
  141. return 0;
  142. }