board_f.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <bloblist.h>
  13. #include <clock_legacy.h>
  14. #include <console.h>
  15. #include <cpu.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <env.h>
  19. #include <env_internal.h>
  20. #include <fdtdec.h>
  21. #include <fs.h>
  22. #include <hang.h>
  23. #include <i2c.h>
  24. #include <init.h>
  25. #include <initcall.h>
  26. #include <lcd.h>
  27. #include <malloc.h>
  28. #include <mapmem.h>
  29. #include <os.h>
  30. #include <post.h>
  31. #include <relocate.h>
  32. #include <serial.h>
  33. #ifdef CONFIG_SPL
  34. #include <spl.h>
  35. #endif
  36. #include <status_led.h>
  37. #include <sysreset.h>
  38. #include <timer.h>
  39. #include <trace.h>
  40. #include <video.h>
  41. #include <watchdog.h>
  42. #ifdef CONFIG_MACH_TYPE
  43. #include <asm/mach-types.h>
  44. #endif
  45. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  46. #include <asm/mp.h>
  47. #endif
  48. #include <asm/io.h>
  49. #include <asm/sections.h>
  50. #include <dm/root.h>
  51. #include <linux/errno.h>
  52. /*
  53. * Pointer to initial global data area
  54. *
  55. * Here we initialize it if needed.
  56. */
  57. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  58. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  59. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  60. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  61. #else
  62. DECLARE_GLOBAL_DATA_PTR;
  63. #endif
  64. /*
  65. * TODO(sjg@chromium.org): IMO this code should be
  66. * refactored to a single function, something like:
  67. *
  68. * void led_set_state(enum led_colour_t colour, int on);
  69. */
  70. /************************************************************************
  71. * Coloured LED functionality
  72. ************************************************************************
  73. * May be supplied by boards if desired
  74. */
  75. __weak void coloured_LED_init(void) {}
  76. __weak void red_led_on(void) {}
  77. __weak void red_led_off(void) {}
  78. __weak void green_led_on(void) {}
  79. __weak void green_led_off(void) {}
  80. __weak void yellow_led_on(void) {}
  81. __weak void yellow_led_off(void) {}
  82. __weak void blue_led_on(void) {}
  83. __weak void blue_led_off(void) {}
  84. /*
  85. * Why is gd allocated a register? Prior to reloc it might be better to
  86. * just pass it around to each function in this file?
  87. *
  88. * After reloc one could argue that it is hardly used and doesn't need
  89. * to be in a register. Or if it is it should perhaps hold pointers to all
  90. * global data for all modules, so that post-reloc we can avoid the massive
  91. * literal pool we get on ARM. Or perhaps just encourage each module to use
  92. * a structure...
  93. */
  94. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  95. static int init_func_watchdog_init(void)
  96. {
  97. # if defined(CONFIG_HW_WATCHDOG) && \
  98. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  99. defined(CONFIG_SH) || \
  100. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  101. defined(CONFIG_IMX_WATCHDOG))
  102. hw_watchdog_init();
  103. puts(" Watchdog enabled\n");
  104. # endif
  105. WATCHDOG_RESET();
  106. return 0;
  107. }
  108. int init_func_watchdog_reset(void)
  109. {
  110. WATCHDOG_RESET();
  111. return 0;
  112. }
  113. #endif /* CONFIG_WATCHDOG */
  114. __weak void board_add_ram_info(int use_default)
  115. {
  116. /* please define platform specific board_add_ram_info() */
  117. }
  118. static int init_baud_rate(void)
  119. {
  120. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  121. return 0;
  122. }
  123. static int display_text_info(void)
  124. {
  125. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  126. ulong bss_start, bss_end, text_base;
  127. bss_start = (ulong)&__bss_start;
  128. bss_end = (ulong)&__bss_end;
  129. #ifdef CONFIG_SYS_TEXT_BASE
  130. text_base = CONFIG_SYS_TEXT_BASE;
  131. #else
  132. text_base = CONFIG_SYS_MONITOR_BASE;
  133. #endif
  134. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  135. text_base, bss_start, bss_end);
  136. #endif
  137. return 0;
  138. }
  139. #ifdef CONFIG_SYSRESET
  140. static int print_resetinfo(void)
  141. {
  142. struct udevice *dev;
  143. char status[256];
  144. int ret;
  145. ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
  146. if (ret) {
  147. debug("%s: No sysreset device found (error: %d)\n",
  148. __func__, ret);
  149. /* Not all boards have sysreset drivers available during early
  150. * boot, so don't fail if one can't be found.
  151. */
  152. return 0;
  153. }
  154. if (!sysreset_get_status(dev, status, sizeof(status)))
  155. printf("%s", status);
  156. return 0;
  157. }
  158. #endif
  159. #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
  160. static int print_cpuinfo(void)
  161. {
  162. struct udevice *dev;
  163. char desc[512];
  164. int ret;
  165. ret = uclass_first_device_err(UCLASS_CPU, &dev);
  166. if (ret) {
  167. debug("%s: Could not get CPU device (err = %d)\n",
  168. __func__, ret);
  169. return ret;
  170. }
  171. ret = cpu_get_desc(dev, desc, sizeof(desc));
  172. if (ret) {
  173. debug("%s: Could not get CPU description (err = %d)\n",
  174. dev->name, ret);
  175. return ret;
  176. }
  177. printf("CPU: %s\n", desc);
  178. return 0;
  179. }
  180. #endif
  181. static int announce_dram_init(void)
  182. {
  183. puts("DRAM: ");
  184. return 0;
  185. }
  186. static int show_dram_config(void)
  187. {
  188. unsigned long long size;
  189. #ifdef CONFIG_NR_DRAM_BANKS
  190. int i;
  191. debug("\nRAM Configuration:\n");
  192. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  193. size += gd->bd->bi_dram[i].size;
  194. debug("Bank #%d: %llx ", i,
  195. (unsigned long long)(gd->bd->bi_dram[i].start));
  196. #ifdef DEBUG
  197. print_size(gd->bd->bi_dram[i].size, "\n");
  198. #endif
  199. }
  200. debug("\nDRAM: ");
  201. #else
  202. size = gd->ram_size;
  203. #endif
  204. print_size(size, "");
  205. board_add_ram_info(0);
  206. putc('\n');
  207. return 0;
  208. }
  209. __weak int dram_init_banksize(void)
  210. {
  211. #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  212. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  213. gd->bd->bi_dram[0].size = get_effective_memsize();
  214. #endif
  215. return 0;
  216. }
  217. #if defined(CONFIG_SYS_I2C)
  218. static int init_func_i2c(void)
  219. {
  220. puts("I2C: ");
  221. #ifdef CONFIG_SYS_I2C
  222. i2c_init_all();
  223. #else
  224. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  225. #endif
  226. puts("ready\n");
  227. return 0;
  228. }
  229. #endif
  230. #if defined(CONFIG_VID)
  231. __weak int init_func_vid(void)
  232. {
  233. return 0;
  234. }
  235. #endif
  236. static int setup_mon_len(void)
  237. {
  238. #if defined(__ARM__) || defined(__MICROBLAZE__)
  239. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  240. #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
  241. gd->mon_len = (ulong)&_end - (ulong)_init;
  242. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  243. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  244. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  245. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  246. #elif defined(CONFIG_SYS_MONITOR_BASE)
  247. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  248. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  249. #endif
  250. return 0;
  251. }
  252. static int setup_spl_handoff(void)
  253. {
  254. #if CONFIG_IS_ENABLED(HANDOFF)
  255. gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
  256. sizeof(struct spl_handoff));
  257. debug("Found SPL hand-off info %p\n", gd->spl_handoff);
  258. #endif
  259. return 0;
  260. }
  261. __weak int arch_cpu_init(void)
  262. {
  263. return 0;
  264. }
  265. __weak int mach_cpu_init(void)
  266. {
  267. return 0;
  268. }
  269. /* Get the top of usable RAM */
  270. __weak ulong board_get_usable_ram_top(ulong total_size)
  271. {
  272. #ifdef CONFIG_SYS_SDRAM_BASE
  273. /*
  274. * Detect whether we have so much RAM that it goes past the end of our
  275. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  276. */
  277. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  278. /*
  279. * Will wrap back to top of 32-bit space when reservations
  280. * are made.
  281. */
  282. return 0;
  283. #endif
  284. return gd->ram_top;
  285. }
  286. static int setup_dest_addr(void)
  287. {
  288. debug("Monitor len: %08lX\n", gd->mon_len);
  289. /*
  290. * Ram is setup, size stored in gd !!
  291. */
  292. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  293. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  294. /*
  295. * Subtract specified amount of memory to hide so that it won't
  296. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  297. * the Linux kernel should now get passed the now "corrected"
  298. * memory size and won't touch it either. This should work
  299. * for arch/ppc and arch/powerpc. Only Linux board ports in
  300. * arch/powerpc with bootwrapper support, that recalculate the
  301. * memory size from the SDRAM controller setup will have to
  302. * get fixed.
  303. */
  304. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  305. #endif
  306. #ifdef CONFIG_SYS_SDRAM_BASE
  307. gd->ram_base = CONFIG_SYS_SDRAM_BASE;
  308. #endif
  309. gd->ram_top = gd->ram_base + get_effective_memsize();
  310. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  311. gd->relocaddr = gd->ram_top;
  312. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  313. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  314. /*
  315. * We need to make sure the location we intend to put secondary core
  316. * boot code is reserved and not used by any part of u-boot
  317. */
  318. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  319. gd->relocaddr = determine_mp_bootpg(NULL);
  320. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  321. }
  322. #endif
  323. return 0;
  324. }
  325. #ifdef CONFIG_PRAM
  326. /* reserve protected RAM */
  327. static int reserve_pram(void)
  328. {
  329. ulong reg;
  330. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  331. gd->relocaddr -= (reg << 10); /* size is in kB */
  332. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  333. gd->relocaddr);
  334. return 0;
  335. }
  336. #endif /* CONFIG_PRAM */
  337. /* Round memory pointer down to next 4 kB limit */
  338. static int reserve_round_4k(void)
  339. {
  340. gd->relocaddr &= ~(4096 - 1);
  341. return 0;
  342. }
  343. #ifdef CONFIG_ARM
  344. __weak int reserve_mmu(void)
  345. {
  346. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  347. /* reserve TLB table */
  348. gd->arch.tlb_size = PGTABLE_SIZE;
  349. gd->relocaddr -= gd->arch.tlb_size;
  350. /* round down to next 64 kB limit */
  351. gd->relocaddr &= ~(0x10000 - 1);
  352. gd->arch.tlb_addr = gd->relocaddr;
  353. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  354. gd->arch.tlb_addr + gd->arch.tlb_size);
  355. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  356. /*
  357. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  358. * with location within secure ram.
  359. */
  360. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  361. #endif
  362. #endif
  363. return 0;
  364. }
  365. #endif
  366. static int reserve_video(void)
  367. {
  368. #ifdef CONFIG_DM_VIDEO
  369. ulong addr;
  370. int ret;
  371. addr = gd->relocaddr;
  372. ret = video_reserve(&addr);
  373. if (ret)
  374. return ret;
  375. gd->relocaddr = addr;
  376. #elif defined(CONFIG_LCD)
  377. # ifdef CONFIG_FB_ADDR
  378. gd->fb_base = CONFIG_FB_ADDR;
  379. # else
  380. /* reserve memory for LCD display (always full pages) */
  381. gd->relocaddr = lcd_setmem(gd->relocaddr);
  382. gd->fb_base = gd->relocaddr;
  383. # endif /* CONFIG_FB_ADDR */
  384. #endif
  385. return 0;
  386. }
  387. static int reserve_trace(void)
  388. {
  389. #ifdef CONFIG_TRACE
  390. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  391. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  392. debug("Reserving %luk for trace data at: %08lx\n",
  393. (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  394. #endif
  395. return 0;
  396. }
  397. static int reserve_uboot(void)
  398. {
  399. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  400. /*
  401. * reserve memory for U-Boot code, data & bss
  402. * round down to next 4 kB limit
  403. */
  404. gd->relocaddr -= gd->mon_len;
  405. gd->relocaddr &= ~(4096 - 1);
  406. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  407. /* round down to next 64 kB limit so that IVPR stays aligned */
  408. gd->relocaddr &= ~(65536 - 1);
  409. #endif
  410. debug("Reserving %ldk for U-Boot at: %08lx\n",
  411. gd->mon_len >> 10, gd->relocaddr);
  412. }
  413. gd->start_addr_sp = gd->relocaddr;
  414. return 0;
  415. }
  416. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  417. static int reserve_noncached(void)
  418. {
  419. /*
  420. * The value of gd->start_addr_sp must match the value of malloc_start
  421. * calculated in boatrd_f.c:initr_malloc(), which is passed to
  422. * board_r.c:mem_malloc_init() and then used by
  423. * cache.c:noncached_init()
  424. *
  425. * These calculations must match the code in cache.c:noncached_init()
  426. */
  427. gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
  428. MMU_SECTION_SIZE;
  429. gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
  430. MMU_SECTION_SIZE);
  431. debug("Reserving %dM for noncached_alloc() at: %08lx\n",
  432. CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
  433. return 0;
  434. }
  435. #endif
  436. /* reserve memory for malloc() area */
  437. static int reserve_malloc(void)
  438. {
  439. gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
  440. debug("Reserving %dk for malloc() at: %08lx\n",
  441. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  442. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  443. reserve_noncached();
  444. #endif
  445. return 0;
  446. }
  447. /* (permanently) allocate a Board Info struct */
  448. static int reserve_board(void)
  449. {
  450. if (!gd->bd) {
  451. gd->start_addr_sp -= sizeof(bd_t);
  452. gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
  453. memset(gd->bd, '\0', sizeof(bd_t));
  454. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  455. sizeof(bd_t), gd->start_addr_sp);
  456. }
  457. return 0;
  458. }
  459. static int setup_machine(void)
  460. {
  461. #ifdef CONFIG_MACH_TYPE
  462. gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  463. #endif
  464. return 0;
  465. }
  466. static int reserve_global_data(void)
  467. {
  468. gd->start_addr_sp -= sizeof(gd_t);
  469. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  470. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  471. sizeof(gd_t), gd->start_addr_sp);
  472. return 0;
  473. }
  474. static int reserve_fdt(void)
  475. {
  476. #ifndef CONFIG_OF_EMBED
  477. /*
  478. * If the device tree is sitting immediately above our image then we
  479. * must relocate it. If it is embedded in the data section, then it
  480. * will be relocated with other data.
  481. */
  482. if (gd->fdt_blob) {
  483. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
  484. gd->start_addr_sp -= gd->fdt_size;
  485. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  486. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  487. gd->fdt_size, gd->start_addr_sp);
  488. }
  489. #endif
  490. return 0;
  491. }
  492. static int reserve_bootstage(void)
  493. {
  494. #ifdef CONFIG_BOOTSTAGE
  495. int size = bootstage_get_size();
  496. gd->start_addr_sp -= size;
  497. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  498. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  499. gd->start_addr_sp);
  500. #endif
  501. return 0;
  502. }
  503. __weak int arch_reserve_stacks(void)
  504. {
  505. return 0;
  506. }
  507. static int reserve_stacks(void)
  508. {
  509. /* make stack pointer 16-byte aligned */
  510. gd->start_addr_sp -= 16;
  511. gd->start_addr_sp &= ~0xf;
  512. /*
  513. * let the architecture-specific code tailor gd->start_addr_sp and
  514. * gd->irq_sp
  515. */
  516. return arch_reserve_stacks();
  517. }
  518. static int reserve_bloblist(void)
  519. {
  520. #ifdef CONFIG_BLOBLIST
  521. gd->start_addr_sp &= ~0xf;
  522. gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
  523. gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
  524. #endif
  525. return 0;
  526. }
  527. static int display_new_sp(void)
  528. {
  529. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  530. return 0;
  531. }
  532. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  533. defined(CONFIG_SH)
  534. static int setup_board_part1(void)
  535. {
  536. bd_t *bd = gd->bd;
  537. /*
  538. * Save local variables to board info struct
  539. */
  540. bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
  541. bd->bi_memsize = gd->ram_size; /* size in bytes */
  542. #ifdef CONFIG_SYS_SRAM_BASE
  543. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  544. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  545. #endif
  546. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  547. bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
  548. #endif
  549. #if defined(CONFIG_M68K)
  550. bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
  551. #endif
  552. #if defined(CONFIG_MPC83xx)
  553. bd->bi_immrbar = CONFIG_SYS_IMMR;
  554. #endif
  555. return 0;
  556. }
  557. #endif
  558. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  559. static int setup_board_part2(void)
  560. {
  561. bd_t *bd = gd->bd;
  562. bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
  563. bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
  564. #if defined(CONFIG_CPM2)
  565. bd->bi_cpmfreq = gd->arch.cpm_clk;
  566. bd->bi_brgfreq = gd->arch.brg_clk;
  567. bd->bi_sccfreq = gd->arch.scc_clk;
  568. bd->bi_vco = gd->arch.vco_out;
  569. #endif /* CONFIG_CPM2 */
  570. #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
  571. bd->bi_pcifreq = gd->pci_clk;
  572. #endif
  573. #if defined(CONFIG_EXTRA_CLOCK)
  574. bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
  575. bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
  576. bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
  577. #endif
  578. return 0;
  579. }
  580. #endif
  581. #ifdef CONFIG_POST
  582. static int init_post(void)
  583. {
  584. post_bootmode_init();
  585. post_run(NULL, POST_ROM | post_bootmode_get(0));
  586. return 0;
  587. }
  588. #endif
  589. static int reloc_fdt(void)
  590. {
  591. #ifndef CONFIG_OF_EMBED
  592. if (gd->flags & GD_FLG_SKIP_RELOC)
  593. return 0;
  594. if (gd->new_fdt) {
  595. memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
  596. gd->fdt_blob = gd->new_fdt;
  597. }
  598. #endif
  599. return 0;
  600. }
  601. static int reloc_bootstage(void)
  602. {
  603. #ifdef CONFIG_BOOTSTAGE
  604. if (gd->flags & GD_FLG_SKIP_RELOC)
  605. return 0;
  606. if (gd->new_bootstage) {
  607. int size = bootstage_get_size();
  608. debug("Copying bootstage from %p to %p, size %x\n",
  609. gd->bootstage, gd->new_bootstage, size);
  610. memcpy(gd->new_bootstage, gd->bootstage, size);
  611. gd->bootstage = gd->new_bootstage;
  612. bootstage_relocate();
  613. }
  614. #endif
  615. return 0;
  616. }
  617. static int reloc_bloblist(void)
  618. {
  619. #ifdef CONFIG_BLOBLIST
  620. if (gd->flags & GD_FLG_SKIP_RELOC)
  621. return 0;
  622. if (gd->new_bloblist) {
  623. int size = CONFIG_BLOBLIST_SIZE;
  624. debug("Copying bloblist from %p to %p, size %x\n",
  625. gd->bloblist, gd->new_bloblist, size);
  626. memcpy(gd->new_bloblist, gd->bloblist, size);
  627. gd->bloblist = gd->new_bloblist;
  628. }
  629. #endif
  630. return 0;
  631. }
  632. static int setup_reloc(void)
  633. {
  634. if (gd->flags & GD_FLG_SKIP_RELOC) {
  635. debug("Skipping relocation due to flag\n");
  636. return 0;
  637. }
  638. #ifdef CONFIG_SYS_TEXT_BASE
  639. #ifdef ARM
  640. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  641. #elif defined(CONFIG_M68K)
  642. /*
  643. * On all ColdFire arch cpu, monitor code starts always
  644. * just after the default vector table location, so at 0x400
  645. */
  646. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  647. #elif !defined(CONFIG_SANDBOX)
  648. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  649. #endif
  650. #endif
  651. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  652. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  653. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  654. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  655. gd->start_addr_sp);
  656. return 0;
  657. }
  658. #ifdef CONFIG_OF_BOARD_FIXUP
  659. static int fix_fdt(void)
  660. {
  661. return board_fix_fdt((void *)gd->fdt_blob);
  662. }
  663. #endif
  664. /* ARM calls relocate_code from its crt0.S */
  665. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  666. !CONFIG_IS_ENABLED(X86_64)
  667. static int jump_to_copy(void)
  668. {
  669. if (gd->flags & GD_FLG_SKIP_RELOC)
  670. return 0;
  671. /*
  672. * x86 is special, but in a nice way. It uses a trampoline which
  673. * enables the dcache if possible.
  674. *
  675. * For now, other archs use relocate_code(), which is implemented
  676. * similarly for all archs. When we do generic relocation, hopefully
  677. * we can make all archs enable the dcache prior to relocation.
  678. */
  679. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  680. /*
  681. * SDRAM and console are now initialised. The final stack can now
  682. * be setup in SDRAM. Code execution will continue in Flash, but
  683. * with the stack in SDRAM and Global Data in temporary memory
  684. * (CPU cache)
  685. */
  686. arch_setup_gd(gd->new_gd);
  687. board_init_f_r_trampoline(gd->start_addr_sp);
  688. #else
  689. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  690. #endif
  691. return 0;
  692. }
  693. #endif
  694. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  695. static int initf_bootstage(void)
  696. {
  697. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  698. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  699. int ret;
  700. ret = bootstage_init(!from_spl);
  701. if (ret)
  702. return ret;
  703. if (from_spl) {
  704. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  705. CONFIG_BOOTSTAGE_STASH_SIZE);
  706. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  707. if (ret && ret != -ENOENT) {
  708. debug("Failed to unstash bootstage: err=%d\n", ret);
  709. return ret;
  710. }
  711. }
  712. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  713. return 0;
  714. }
  715. static int initf_console_record(void)
  716. {
  717. #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  718. return console_record_init();
  719. #else
  720. return 0;
  721. #endif
  722. }
  723. static int initf_dm(void)
  724. {
  725. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  726. int ret;
  727. bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
  728. ret = dm_init_and_scan(true);
  729. bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
  730. if (ret)
  731. return ret;
  732. #endif
  733. #ifdef CONFIG_TIMER_EARLY
  734. ret = dm_timer_init();
  735. if (ret)
  736. return ret;
  737. #endif
  738. return 0;
  739. }
  740. /* Architecture-specific memory reservation */
  741. __weak int reserve_arch(void)
  742. {
  743. return 0;
  744. }
  745. __weak int arch_cpu_init_dm(void)
  746. {
  747. return 0;
  748. }
  749. static const init_fnc_t init_sequence_f[] = {
  750. setup_mon_len,
  751. #ifdef CONFIG_OF_CONTROL
  752. fdtdec_setup,
  753. #endif
  754. #ifdef CONFIG_TRACE_EARLY
  755. trace_early_init,
  756. #endif
  757. initf_malloc,
  758. log_init,
  759. initf_bootstage, /* uses its own timer, so does not need DM */
  760. #ifdef CONFIG_BLOBLIST
  761. bloblist_init,
  762. #endif
  763. setup_spl_handoff,
  764. initf_console_record,
  765. #if defined(CONFIG_HAVE_FSP)
  766. arch_fsp_init,
  767. #endif
  768. arch_cpu_init, /* basic arch cpu dependent setup */
  769. mach_cpu_init, /* SoC/machine dependent CPU setup */
  770. initf_dm,
  771. arch_cpu_init_dm,
  772. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  773. board_early_init_f,
  774. #endif
  775. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  776. /* get CPU and bus clocks according to the environment variable */
  777. get_clocks, /* get CPU and bus clocks (etc.) */
  778. #endif
  779. #if !defined(CONFIG_M68K)
  780. timer_init, /* initialize timer */
  781. #endif
  782. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  783. board_postclk_init,
  784. #endif
  785. env_init, /* initialize environment */
  786. init_baud_rate, /* initialze baudrate settings */
  787. serial_init, /* serial communications setup */
  788. console_init_f, /* stage 1 init of console */
  789. display_options, /* say that we are here */
  790. display_text_info, /* show debugging info if required */
  791. #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
  792. checkcpu,
  793. #endif
  794. #if defined(CONFIG_SYSRESET)
  795. print_resetinfo,
  796. #endif
  797. #if defined(CONFIG_DISPLAY_CPUINFO)
  798. print_cpuinfo, /* display cpu info (and speed) */
  799. #endif
  800. #if defined(CONFIG_DTB_RESELECT)
  801. embedded_dtb_select,
  802. #endif
  803. #if defined(CONFIG_DISPLAY_BOARDINFO)
  804. show_board_info,
  805. #endif
  806. INIT_FUNC_WATCHDOG_INIT
  807. #if defined(CONFIG_MISC_INIT_F)
  808. misc_init_f,
  809. #endif
  810. INIT_FUNC_WATCHDOG_RESET
  811. #if defined(CONFIG_SYS_I2C)
  812. init_func_i2c,
  813. #endif
  814. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  815. init_func_vid,
  816. #endif
  817. announce_dram_init,
  818. dram_init, /* configure available RAM banks */
  819. #ifdef CONFIG_POST
  820. post_init_f,
  821. #endif
  822. INIT_FUNC_WATCHDOG_RESET
  823. #if defined(CONFIG_SYS_DRAM_TEST)
  824. testdram,
  825. #endif /* CONFIG_SYS_DRAM_TEST */
  826. INIT_FUNC_WATCHDOG_RESET
  827. #ifdef CONFIG_POST
  828. init_post,
  829. #endif
  830. INIT_FUNC_WATCHDOG_RESET
  831. /*
  832. * Now that we have DRAM mapped and working, we can
  833. * relocate the code and continue running from DRAM.
  834. *
  835. * Reserve memory at end of RAM for (top down in that order):
  836. * - area that won't get touched by U-Boot and Linux (optional)
  837. * - kernel log buffer
  838. * - protected RAM
  839. * - LCD framebuffer
  840. * - monitor code
  841. * - board info struct
  842. */
  843. setup_dest_addr,
  844. #ifdef CONFIG_PRAM
  845. reserve_pram,
  846. #endif
  847. reserve_round_4k,
  848. #ifdef CONFIG_ARM
  849. reserve_mmu,
  850. #endif
  851. reserve_video,
  852. reserve_trace,
  853. reserve_uboot,
  854. reserve_malloc,
  855. reserve_board,
  856. setup_machine,
  857. reserve_global_data,
  858. reserve_fdt,
  859. reserve_bootstage,
  860. reserve_bloblist,
  861. reserve_arch,
  862. reserve_stacks,
  863. dram_init_banksize,
  864. show_dram_config,
  865. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  866. defined(CONFIG_SH)
  867. setup_board_part1,
  868. #endif
  869. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  870. INIT_FUNC_WATCHDOG_RESET
  871. setup_board_part2,
  872. #endif
  873. display_new_sp,
  874. #ifdef CONFIG_OF_BOARD_FIXUP
  875. fix_fdt,
  876. #endif
  877. INIT_FUNC_WATCHDOG_RESET
  878. reloc_fdt,
  879. reloc_bootstage,
  880. reloc_bloblist,
  881. setup_reloc,
  882. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  883. copy_uboot_to_ram,
  884. do_elf_reloc_fixups,
  885. clear_bss,
  886. #endif
  887. #if defined(CONFIG_XTENSA)
  888. clear_bss,
  889. #endif
  890. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  891. !CONFIG_IS_ENABLED(X86_64)
  892. jump_to_copy,
  893. #endif
  894. NULL,
  895. };
  896. void board_init_f(ulong boot_flags)
  897. {
  898. gd->flags = boot_flags;
  899. gd->have_console = 0;
  900. if (initcall_run_list(init_sequence_f))
  901. hang();
  902. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  903. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  904. !defined(CONFIG_ARC)
  905. /* NOTREACHED - jump_to_copy() does not return */
  906. hang();
  907. #endif
  908. }
  909. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  910. /*
  911. * For now this code is only used on x86.
  912. *
  913. * init_sequence_f_r is the list of init functions which are run when
  914. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  915. * The following limitations must be considered when implementing an
  916. * '_f_r' function:
  917. * - 'static' variables are read-only
  918. * - Global Data (gd->xxx) is read/write
  919. *
  920. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  921. * supported). It _should_, if possible, copy global data to RAM and
  922. * initialise the CPU caches (to speed up the relocation process)
  923. *
  924. * NOTE: At present only x86 uses this route, but it is intended that
  925. * all archs will move to this when generic relocation is implemented.
  926. */
  927. static const init_fnc_t init_sequence_f_r[] = {
  928. #if !CONFIG_IS_ENABLED(X86_64)
  929. init_cache_f_r,
  930. #endif
  931. NULL,
  932. };
  933. void board_init_f_r(void)
  934. {
  935. if (initcall_run_list(init_sequence_f_r))
  936. hang();
  937. /*
  938. * The pre-relocation drivers may be using memory that has now gone
  939. * away. Mark serial as unavailable - this will fall back to the debug
  940. * UART if available.
  941. *
  942. * Do the same with log drivers since the memory may not be available.
  943. */
  944. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  945. #ifdef CONFIG_TIMER
  946. gd->timer = NULL;
  947. #endif
  948. /*
  949. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  950. * Transfer execution from Flash to RAM by calculating the address
  951. * of the in-RAM copy of board_init_r() and calling it
  952. */
  953. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  954. /* NOTREACHED - board_init_r() does not return */
  955. hang();
  956. }
  957. #endif /* CONFIG_X86 */