board.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone : Board initialization
  4. *
  5. * (C) Copyright 2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include "board.h"
  10. #include <env.h>
  11. #include <hang.h>
  12. #include <init.h>
  13. #include <spl.h>
  14. #include <exports.h>
  15. #include <fdt_support.h>
  16. #include <asm/arch/ddr3.h>
  17. #include <asm/arch/psc_defs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/ti-common/ti-aemif.h>
  20. #include <asm/ti-common/keystone_net.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #if defined(CONFIG_TI_AEMIF)
  23. static struct aemif_config aemif_configs[] = {
  24. { /* CS0 */
  25. .mode = AEMIF_MODE_NAND,
  26. .wr_setup = 0xf,
  27. .wr_strobe = 0x3f,
  28. .wr_hold = 7,
  29. .rd_setup = 0xf,
  30. .rd_strobe = 0x3f,
  31. .rd_hold = 7,
  32. .turn_around = 3,
  33. .width = AEMIF_WIDTH_8,
  34. },
  35. };
  36. #endif
  37. int dram_init(void)
  38. {
  39. u32 ddr3_size;
  40. ddr3_size = ddr3_init();
  41. gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  42. CONFIG_MAX_RAM_BANK_SIZE);
  43. #if defined(CONFIG_TI_AEMIF)
  44. if (!board_is_k2g_ice())
  45. aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  46. #endif
  47. if (!board_is_k2g_ice()) {
  48. if (ddr3_size)
  49. ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  50. else
  51. ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  52. gd->ram_size >> 30);
  53. }
  54. return 0;
  55. }
  56. struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  57. {
  58. return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  59. }
  60. int board_init(void)
  61. {
  62. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  63. return 0;
  64. }
  65. #ifdef CONFIG_SPL_BUILD
  66. void spl_board_init(void)
  67. {
  68. spl_init_keystone_plls();
  69. preloader_console_init();
  70. }
  71. u32 spl_boot_device(void)
  72. {
  73. #if defined(CONFIG_SPL_SPI_LOAD)
  74. return BOOT_DEVICE_SPI;
  75. #else
  76. puts("Unknown boot device\n");
  77. hang();
  78. #endif
  79. }
  80. #endif
  81. #ifdef CONFIG_OF_BOARD_SETUP
  82. int ft_board_setup(void *blob, bd_t *bd)
  83. {
  84. int lpae;
  85. char *env;
  86. char *endp;
  87. int nbanks;
  88. u64 size[2];
  89. u64 start[2];
  90. u32 ddr3a_size;
  91. env = env_get("mem_lpae");
  92. lpae = env && simple_strtol(env, NULL, 0);
  93. ddr3a_size = 0;
  94. if (lpae) {
  95. ddr3a_size = ddr3_get_size();
  96. if ((ddr3a_size != 8) && (ddr3a_size != 4))
  97. ddr3a_size = 0;
  98. }
  99. nbanks = 1;
  100. start[0] = bd->bi_dram[0].start;
  101. size[0] = bd->bi_dram[0].size;
  102. /* adjust memory start address for LPAE */
  103. if (lpae) {
  104. start[0] -= CONFIG_SYS_SDRAM_BASE;
  105. start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
  106. }
  107. if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
  108. size[1] = ((u64)ddr3a_size - 2) << 30;
  109. start[1] = 0x880000000;
  110. nbanks++;
  111. }
  112. /* reserve memory at start of bank */
  113. env = env_get("mem_reserve_head");
  114. if (env) {
  115. start[0] += ustrtoul(env, &endp, 0);
  116. size[0] -= ustrtoul(env, &endp, 0);
  117. }
  118. env = env_get("mem_reserve");
  119. if (env)
  120. size[0] -= ustrtoul(env, &endp, 0);
  121. fdt_fixup_memory_banks(blob, start, size, nbanks);
  122. return 0;
  123. }
  124. void ft_board_setup_ex(void *blob, bd_t *bd)
  125. {
  126. int lpae;
  127. u64 size;
  128. char *env;
  129. u64 *reserve_start;
  130. int unitrd_fixup = 0;
  131. env = env_get("mem_lpae");
  132. lpae = env && simple_strtol(env, NULL, 0);
  133. env = env_get("uinitrd_fixup");
  134. unitrd_fixup = env && simple_strtol(env, NULL, 0);
  135. /* Fix up the initrd */
  136. if (lpae && unitrd_fixup) {
  137. int nodeoffset;
  138. int err;
  139. u64 *prop1, *prop2;
  140. u64 initrd_start, initrd_end;
  141. nodeoffset = fdt_path_offset(blob, "/chosen");
  142. if (nodeoffset >= 0) {
  143. prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
  144. "linux,initrd-start", NULL);
  145. prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
  146. "linux,initrd-end", NULL);
  147. if (prop1 && prop2) {
  148. initrd_start = __be64_to_cpu(*prop1);
  149. initrd_start -= CONFIG_SYS_SDRAM_BASE;
  150. initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
  151. initrd_start = __cpu_to_be64(initrd_start);
  152. initrd_end = __be64_to_cpu(*prop2);
  153. initrd_end -= CONFIG_SYS_SDRAM_BASE;
  154. initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
  155. initrd_end = __cpu_to_be64(initrd_end);
  156. err = fdt_delprop(blob, nodeoffset,
  157. "linux,initrd-start");
  158. if (err < 0)
  159. puts("error deleting initrd-start\n");
  160. err = fdt_delprop(blob, nodeoffset,
  161. "linux,initrd-end");
  162. if (err < 0)
  163. puts("error deleting initrd-end\n");
  164. err = fdt_setprop(blob, nodeoffset,
  165. "linux,initrd-start",
  166. &initrd_start,
  167. sizeof(initrd_start));
  168. if (err < 0)
  169. puts("error adding initrd-start\n");
  170. err = fdt_setprop(blob, nodeoffset,
  171. "linux,initrd-end",
  172. &initrd_end,
  173. sizeof(initrd_end));
  174. if (err < 0)
  175. puts("error adding linux,initrd-end\n");
  176. }
  177. }
  178. }
  179. if (lpae) {
  180. /*
  181. * the initrd and other reserved memory areas are
  182. * embedded in in the DTB itslef. fix up these addresses
  183. * to 36 bit format
  184. */
  185. reserve_start = (u64 *)((char *)blob +
  186. fdt_off_mem_rsvmap(blob));
  187. while (1) {
  188. *reserve_start = __cpu_to_be64(*reserve_start);
  189. size = __cpu_to_be64(*(reserve_start + 1));
  190. if (size) {
  191. *reserve_start -= CONFIG_SYS_SDRAM_BASE;
  192. *reserve_start +=
  193. CONFIG_SYS_LPAE_SDRAM_BASE;
  194. *reserve_start =
  195. __cpu_to_be64(*reserve_start);
  196. } else {
  197. break;
  198. }
  199. reserve_start += 2;
  200. }
  201. }
  202. ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
  203. }
  204. #endif /* CONFIG_OF_BOARD_SETUP */
  205. #if defined(CONFIG_DTB_RESELECT)
  206. int __weak embedded_dtb_select(void)
  207. {
  208. return 0;
  209. }
  210. #endif