spl.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <cpu_func.h>
  4. #include <hang.h>
  5. #include <init.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/mx6ul_pins.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <linux/libfdt.h>
  18. #include <spl.h>
  19. #if defined(CONFIG_SPL_BUILD)
  20. #ifdef CONFIG_SPL_OS_BOOT
  21. int spl_start_uboot(void)
  22. {
  23. /* Break into full U-Boot on 'c' */
  24. if (serial_tstc() && serial_getc() == 'c')
  25. return 1;
  26. return 0;
  27. }
  28. #endif
  29. #include <asm/arch/mx6-ddr.h>
  30. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  31. .grp_addds = 0x00000030,
  32. .grp_ddrmode_ctl = 0x00020000,
  33. .grp_b0ds = 0x00000030,
  34. .grp_ctlds = 0x00000030,
  35. .grp_b1ds = 0x00000030,
  36. .grp_ddrpke = 0x00000000,
  37. .grp_ddrmode = 0x00020000,
  38. .grp_ddr_type = 0x00080000,
  39. };
  40. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  41. .dram_dqm0 = 0x00000030,
  42. .dram_dqm1 = 0x00000030,
  43. .dram_ras = 0x00000030,
  44. .dram_cas = 0x00000030,
  45. .dram_odt0 = 0x00000030,
  46. .dram_odt1 = 0x00000030,
  47. .dram_sdba2 = 0x00000000,
  48. .dram_sdclk_0 = 0x00000030,
  49. .dram_sdqs0 = 0x00000030,
  50. .dram_sdqs1 = 0x00000030,
  51. .dram_reset = 0x00000030,
  52. };
  53. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  54. .p0_mpwldectrl0 = 0x00000000,
  55. .p0_mpdgctrl0 = 0x01380134,
  56. .p0_mprddlctl = 0x40404244,
  57. .p0_mpwrdlctl = 0x40405050,
  58. };
  59. static struct mx6_ddr_sysinfo ddr_sysinfo = {
  60. .dsize = 0,
  61. .cs1_mirror = 0,
  62. .cs_density = 32,
  63. .ncs = 1,
  64. .bi_on = 1,
  65. .rtt_nom = 1,
  66. .rtt_wr = 0,
  67. .ralat = 5,
  68. .walat = 0,
  69. .mif3_mode = 3,
  70. .rst_to_cke = 0x23,
  71. .sde_to_rst = 0x10,
  72. .refsel = 1,
  73. .refr = 3,
  74. };
  75. static struct mx6_ddr3_cfg mem_ddr = {
  76. .mem_speed = 1333,
  77. .density = 2,
  78. .width = 16,
  79. .banks = 8,
  80. .coladdr = 10,
  81. .pagesz = 2,
  82. .trcd = 1350,
  83. .trcmin = 4950,
  84. .trasmin = 3600,
  85. };
  86. static void ccgr_init(void)
  87. {
  88. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  89. writel(0xFFFFFFFF, &ccm->CCGR0);
  90. writel(0xFFFFFFFF, &ccm->CCGR1);
  91. writel(0xFFFFFFFF, &ccm->CCGR2);
  92. writel(0xFFFFFFFF, &ccm->CCGR3);
  93. writel(0xFFFFFFFF, &ccm->CCGR4);
  94. writel(0xFFFFFFFF, &ccm->CCGR5);
  95. writel(0xFFFFFFFF, &ccm->CCGR6);
  96. }
  97. static void imx6ul_spl_dram_cfg_size(u32 ram_size)
  98. {
  99. if (ram_size == SZ_256M)
  100. mem_ddr.rowaddr = 14;
  101. else
  102. mem_ddr.rowaddr = 15;
  103. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  104. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  105. }
  106. static void imx6ul_spl_dram_cfg(void)
  107. {
  108. ulong ram_size_test, ram_size = 0;
  109. for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
  110. imx6ul_spl_dram_cfg_size(ram_size);
  111. ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
  112. if (ram_size_test == ram_size)
  113. break;
  114. }
  115. if (ram_size < SZ_256M) {
  116. puts("ERROR: DRAM size detection failed\n");
  117. hang();
  118. }
  119. }
  120. void board_init_f(ulong dummy)
  121. {
  122. ccgr_init();
  123. arch_cpu_init();
  124. board_early_init_f();
  125. timer_init();
  126. preloader_console_init();
  127. imx6ul_spl_dram_cfg();
  128. memset(__bss_start, 0, __bss_end - __bss_start);
  129. board_init_r(NULL, 0);
  130. }
  131. void reset_cpu(ulong addr)
  132. {
  133. }
  134. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  135. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  136. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  137. static iomux_v3_cfg_t const usdhc1_pads[] = {
  138. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  142. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  143. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  144. MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  145. MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  146. MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  147. MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  148. };
  149. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  150. {USDHC1_BASE_ADDR},
  151. };
  152. int board_mmc_getcd(struct mmc *mmc)
  153. {
  154. return 1;
  155. }
  156. int board_mmc_init(bd_t *bis)
  157. {
  158. imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  159. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  160. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  161. }
  162. #endif