porter.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/porter/porter.c
  4. *
  5. * Copyright (C) 2015 Renesas Electronics Corporation
  6. * Copyright (C) 2015 Cogent Embedded, Inc.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <env.h>
  11. #include <hang.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #include <dm/platform_data/serial_sh.h>
  15. #include <env_internal.h>
  16. #include <asm/processor.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/io.h>
  19. #include <linux/errno.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/gpio.h>
  22. #include <asm/arch/rmobile.h>
  23. #include <asm/arch/rcar-mstp.h>
  24. #include <asm/arch/sh_sdhi.h>
  25. #include <netdev.h>
  26. #include <miiphy.h>
  27. #include <i2c.h>
  28. #include <div64.h>
  29. #include "qos.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  32. void s_init(void)
  33. {
  34. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  35. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  36. u32 stc;
  37. /* Watchdog init */
  38. writel(0xA5A5A500, &rwdt->rwtcsra);
  39. writel(0xA5A5A500, &swdt->swtcsra);
  40. /* CPU frequency setting. Set to 1.5GHz */
  41. stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  42. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  43. /* QoS */
  44. qos_init();
  45. }
  46. #define TMU0_MSTP125 BIT(25)
  47. #define SD2CKCR 0xE615026C
  48. #define SD_97500KHZ 0x7
  49. int board_early_init_f(void)
  50. {
  51. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  52. /*
  53. * SD0 clock is set to 97.5MHz by default.
  54. * Set SD2 to the 97.5MHz as well.
  55. */
  56. writel(SD_97500KHZ, SD2CKCR);
  57. return 0;
  58. }
  59. #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
  60. int board_init(void)
  61. {
  62. /* adress of boot parameters */
  63. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  64. /* Force ethernet PHY out of reset */
  65. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  66. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  67. mdelay(10);
  68. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  69. return 0;
  70. }
  71. int dram_init(void)
  72. {
  73. if (fdtdec_setup_mem_size_base() != 0)
  74. return -EINVAL;
  75. return 0;
  76. }
  77. int dram_init_banksize(void)
  78. {
  79. fdtdec_setup_memory_banksize();
  80. return 0;
  81. }
  82. /* porter has KSZ8041RNLI */
  83. #define PHY_CONTROL1 0x1E
  84. #define PHY_LED_MODE 0xC000
  85. #define PHY_LED_MODE_ACK 0x4000
  86. int board_phy_config(struct phy_device *phydev)
  87. {
  88. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  89. ret &= ~PHY_LED_MODE;
  90. ret |= PHY_LED_MODE_ACK;
  91. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  92. return 0;
  93. }
  94. void reset_cpu(ulong addr)
  95. {
  96. struct udevice *dev;
  97. const u8 pmic_bus = 6;
  98. const u8 pmic_addr = 0x5a;
  99. u8 data;
  100. int ret;
  101. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  102. if (ret)
  103. hang();
  104. ret = dm_i2c_read(dev, 0x13, &data, 1);
  105. if (ret)
  106. hang();
  107. data |= BIT(1);
  108. ret = dm_i2c_write(dev, 0x13, &data, 1);
  109. if (ret)
  110. hang();
  111. }
  112. enum env_location env_get_location(enum env_operation op, int prio)
  113. {
  114. const u32 load_magic = 0xb33fc0de;
  115. /* Block environment access if loaded using JTAG */
  116. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  117. (op != ENVOP_INIT))
  118. return ENVL_UNKNOWN;
  119. if (prio)
  120. return ENVL_UNKNOWN;
  121. return ENVL_SPI_FLASH;
  122. }