lager.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/lager/lager.c
  4. * This file is lager board support.
  5. *
  6. * Copyright (C) 2013 Renesas Electronics Corporation
  7. * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <env.h>
  12. #include <env_internal.h>
  13. #include <hang.h>
  14. #include <malloc.h>
  15. #include <netdev.h>
  16. #include <dm.h>
  17. #include <dm/platform_data/serial_sh.h>
  18. #include <asm/processor.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/io.h>
  21. #include <linux/errno.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/gpio.h>
  24. #include <asm/arch/rmobile.h>
  25. #include <asm/arch/rcar-mstp.h>
  26. #include <asm/arch/mmc.h>
  27. #include <asm/arch/sh_sdhi.h>
  28. #include <miiphy.h>
  29. #include <i2c.h>
  30. #include <mmc.h>
  31. #include "qos.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  34. void s_init(void)
  35. {
  36. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  37. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  38. /* Watchdog init */
  39. writel(0xA5A5A500, &rwdt->rwtcsra);
  40. writel(0xA5A5A500, &swdt->swtcsra);
  41. /* CPU frequency setting. Set to 1.4GHz */
  42. if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
  43. u32 stat = 0;
  44. u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
  45. << PLL0_STC_BIT;
  46. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  47. do {
  48. stat = readl(PLLECR) & PLL0ST;
  49. } while (stat == 0x0);
  50. }
  51. /* QoS(Quality-of-Service) Init */
  52. qos_init();
  53. }
  54. #define TMU0_MSTP125 BIT(25)
  55. #define SD1CKCR 0xE6150078
  56. #define SD2CKCR 0xE615026C
  57. #define SD_97500KHZ 0x7
  58. int board_early_init_f(void)
  59. {
  60. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  61. /*
  62. * SD0 clock is set to 97.5MHz by default.
  63. * Set SD1 and SD2 to the 97.5MHz as well.
  64. */
  65. writel(SD_97500KHZ, SD1CKCR);
  66. writel(SD_97500KHZ, SD2CKCR);
  67. return 0;
  68. }
  69. #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
  70. int board_init(void)
  71. {
  72. /* adress of boot parameters */
  73. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  74. /* Force ethernet PHY out of reset */
  75. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  76. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  77. mdelay(10);
  78. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  79. return 0;
  80. }
  81. int dram_init(void)
  82. {
  83. if (fdtdec_setup_mem_size_base() != 0)
  84. return -EINVAL;
  85. return 0;
  86. }
  87. int dram_init_banksize(void)
  88. {
  89. fdtdec_setup_memory_banksize();
  90. return 0;
  91. }
  92. /* KSZ8041NL/RNL */
  93. #define PHY_CONTROL1 0x1E
  94. #define PHY_LED_MODE 0xC000
  95. #define PHY_LED_MODE_ACK 0x4000
  96. int board_phy_config(struct phy_device *phydev)
  97. {
  98. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  99. ret &= ~PHY_LED_MODE;
  100. ret |= PHY_LED_MODE_ACK;
  101. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  102. return 0;
  103. }
  104. void reset_cpu(ulong addr)
  105. {
  106. struct udevice *dev;
  107. const u8 pmic_bus = 2;
  108. const u8 pmic_addr = 0x58;
  109. u8 data;
  110. int ret;
  111. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  112. if (ret)
  113. hang();
  114. ret = dm_i2c_read(dev, 0x13, &data, 1);
  115. if (ret)
  116. hang();
  117. data |= BIT(1);
  118. ret = dm_i2c_write(dev, 0x13, &data, 1);
  119. if (ret)
  120. hang();
  121. }
  122. enum env_location env_get_location(enum env_operation op, int prio)
  123. {
  124. const u32 load_magic = 0xb33fc0de;
  125. /* Block environment access if loaded using JTAG */
  126. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  127. (op != ENVOP_INIT))
  128. return ENVL_UNKNOWN;
  129. if (prio)
  130. return ENVL_UNKNOWN;
  131. return ENVL_SPI_FLASH;
  132. }