draak.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board/renesas/draak/draak.c
  4. * This file is Draak board support.
  5. *
  6. * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <hang.h>
  11. #include <malloc.h>
  12. #include <netdev.h>
  13. #include <dm.h>
  14. #include <dm/platform_data/serial_sh.h>
  15. #include <asm/processor.h>
  16. #include <asm/mach-types.h>
  17. #include <asm/io.h>
  18. #include <linux/errno.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/gpio.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/rmobile.h>
  23. #include <asm/arch/rcar-mstp.h>
  24. #include <asm/arch/sh_sdhi.h>
  25. #include <i2c.h>
  26. #include <mmc.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. void s_init(void)
  29. {
  30. }
  31. #define GSX_MSTP112 BIT(12) /* 3DG */
  32. #define SCIF2_MSTP310 BIT(10) /* SCIF2 */
  33. #define DVFS_MSTP926 BIT(26)
  34. #define HSUSB_MSTP704 BIT(4) /* HSUSB */
  35. int board_early_init_f(void)
  36. {
  37. #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
  38. /* DVFS for reset */
  39. mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
  40. #endif
  41. return 0;
  42. }
  43. /* HSUSB block registers */
  44. #define HSUSB_REG_LPSTS 0xE6590102
  45. #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
  46. #define HSUSB_REG_UGCTRL2 0xE6590184
  47. #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
  48. #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
  49. int board_init(void)
  50. {
  51. /* adress of boot parameters */
  52. gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  53. /* USB1 pull-up */
  54. setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
  55. /* Configure the HSUSB block */
  56. mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
  57. /* Choice USB0SEL */
  58. clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
  59. HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
  60. /* low power status */
  61. setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
  62. return 0;
  63. }
  64. #define RST_BASE 0xE6160000
  65. #define RST_CA57RESCNT (RST_BASE + 0x40)
  66. #define RST_CA53RESCNT (RST_BASE + 0x44)
  67. #define RST_RSTOUTCR (RST_BASE + 0x58)
  68. #define RST_CA57_CODE 0xA5A5000F
  69. #define RST_CA53_CODE 0x5A5A000F
  70. void reset_cpu(ulong addr)
  71. {
  72. unsigned long midr, cputype;
  73. asm volatile("mrs %0, midr_el1" : "=r" (midr));
  74. cputype = (midr >> 4) & 0xfff;
  75. if (cputype == 0xd03)
  76. writel(RST_CA53_CODE, RST_CA53RESCNT);
  77. else if (cputype == 0xd07)
  78. writel(RST_CA57_CODE, RST_CA57RESCNT);
  79. else
  80. hang();
  81. }