p1_p2_rdb_pc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <hang.h>
  9. #include <hwconfig.h>
  10. #include <init.h>
  11. #include <pci.h>
  12. #include <i2c.h>
  13. #include <asm/processor.h>
  14. #include <asm/mmu.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_pci.h>
  18. #include <fsl_ddr_sdram.h>
  19. #include <asm/io.h>
  20. #include <asm/fsl_law.h>
  21. #include <asm/fsl_lbc.h>
  22. #include <asm/mp.h>
  23. #include <miiphy.h>
  24. #include <linux/libfdt.h>
  25. #include <fdt_support.h>
  26. #include <fsl_mdio.h>
  27. #include <tsec.h>
  28. #include <vsc7385.h>
  29. #include <ioports.h>
  30. #include <asm/fsl_serdes.h>
  31. #include <netdev.h>
  32. #ifdef CONFIG_QE
  33. #define GPIO_GETH_SW_PORT 1
  34. #define GPIO_GETH_SW_PIN 29
  35. #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
  36. #define GPIO_SLIC_PORT 1
  37. #define GPIO_SLIC_PIN 30
  38. #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
  39. #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  40. #define GPIO_DDR_RST_PORT 1
  41. #define GPIO_DDR_RST_PIN 8
  42. #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
  43. #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
  44. #endif
  45. #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
  46. #define PCA_IOPORT_I2C_ADDR 0x23
  47. #define PCA_IOPORT_OUTPUT_CMD 0x2
  48. #define PCA_IOPORT_CFG_CMD 0x6
  49. #define PCA_IOPORT_QE_PIN_ENABLE 0xf8
  50. #define PCA_IOPORT_QE_TDM_ENABLE 0xf6
  51. #endif
  52. const qe_iop_conf_t qe_iop_conf_tab[] = {
  53. /* GPIO */
  54. {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
  55. #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  56. {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
  57. #endif
  58. {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
  59. {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
  60. {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
  61. #ifdef CONFIG_TARGET_P1025RDB
  62. /* QE_MUX_MDC */
  63. {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
  64. /* QE_MUX_MDIO */
  65. {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
  66. /* UCC_1_MII */
  67. {0, 23, 2, 0, 2}, /* CLK12 */
  68. {0, 24, 2, 0, 1}, /* CLK9 */
  69. {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
  70. {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
  71. {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
  72. {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  73. {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
  74. {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
  75. {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  76. {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  77. {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  78. {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
  79. {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
  80. {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
  81. {0, 17, 2, 0, 2}, /* ENET1_CRS */
  82. {0, 16, 2, 0, 2}, /* ENET1_COL */
  83. /* UCC_5_RMII */
  84. {1, 11, 2, 0, 1}, /* CLK13 */
  85. {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
  86. {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
  87. {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
  88. {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
  89. {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
  90. {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
  91. {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
  92. #endif
  93. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  94. };
  95. #endif
  96. struct cpld_data {
  97. u8 cpld_rev_major;
  98. u8 pcba_rev;
  99. u8 wd_cfg;
  100. u8 rst_bps_sw;
  101. u8 load_default_n;
  102. u8 rst_bps_wd;
  103. u8 bypass_enable;
  104. u8 bps_led;
  105. u8 status_led; /* offset: 0x8 */
  106. u8 fxo_led; /* offset: 0x9 */
  107. u8 fxs_led; /* offset: 0xa */
  108. u8 rev4[2];
  109. u8 system_rst; /* offset: 0xd */
  110. u8 bps_out;
  111. u8 rev5[3];
  112. u8 cpld_rev_minor;
  113. };
  114. #define CPLD_WD_CFG 0x03
  115. #define CPLD_RST_BSW 0x00
  116. #define CPLD_RST_BWD 0x00
  117. #define CPLD_BYPASS_EN 0x03
  118. #define CPLD_STATUS_LED 0x01
  119. #define CPLD_FXO_LED 0x01
  120. #define CPLD_FXS_LED 0x0F
  121. #define CPLD_SYS_RST 0x00
  122. void board_cpld_init(void)
  123. {
  124. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  125. out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
  126. out_8(&cpld_data->status_led, CPLD_STATUS_LED);
  127. out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
  128. out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
  129. out_8(&cpld_data->system_rst, CPLD_SYS_RST);
  130. }
  131. void board_gpio_init(void)
  132. {
  133. #ifdef CONFIG_QE
  134. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  135. par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
  136. #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  137. /* reset DDR3 */
  138. setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
  139. udelay(1000);
  140. clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
  141. udelay(1000);
  142. setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
  143. /* disable CE_PB8 */
  144. clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
  145. #endif
  146. /* Enable VSC7385 switch */
  147. setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
  148. /* Enable SLIC */
  149. setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
  150. #else
  151. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  152. /*
  153. * GPIO10 DDR Reset, open drain
  154. * GPIO7 LOAD_DEFAULT_N Input
  155. * GPIO11 WDI (watchdog input)
  156. * GPIO12 Ethernet Switch Reset
  157. * GPIO13 SLIC Reset
  158. */
  159. setbits_be32(&pgpio->gpdir, 0x02130000);
  160. #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
  161. /* init DDR3 reset signal */
  162. setbits_be32(&pgpio->gpdir, 0x00200000);
  163. setbits_be32(&pgpio->gpodr, 0x00200000);
  164. clrbits_be32(&pgpio->gpdat, 0x00200000);
  165. udelay(1000);
  166. setbits_be32(&pgpio->gpdat, 0x00200000);
  167. udelay(1000);
  168. clrbits_be32(&pgpio->gpdir, 0x00200000);
  169. #endif
  170. #ifdef CONFIG_VSC7385_ENET
  171. /* reset VSC7385 Switch */
  172. setbits_be32(&pgpio->gpdir, 0x00080000);
  173. setbits_be32(&pgpio->gpdat, 0x00080000);
  174. #endif
  175. #ifdef CONFIG_SLIC
  176. /* reset SLIC */
  177. setbits_be32(&pgpio->gpdir, 0x00040000);
  178. setbits_be32(&pgpio->gpdat, 0x00040000);
  179. #endif
  180. #endif
  181. }
  182. int board_early_init_f(void)
  183. {
  184. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  185. setbits_be32(&gur->pmuxcr,
  186. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  187. clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
  188. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  189. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
  190. board_gpio_init();
  191. board_cpld_init();
  192. return 0;
  193. }
  194. int checkboard(void)
  195. {
  196. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  197. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  198. u8 in, out, io_config, val;
  199. printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
  200. in_8(&cpld_data->cpld_rev_major) & 0x0F,
  201. in_8(&cpld_data->cpld_rev_minor) & 0x0F,
  202. in_8(&cpld_data->pcba_rev) & 0x0F);
  203. /* Initialize i2c early for rom_loc and flash bank information */
  204. i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  205. if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
  206. i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
  207. i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
  208. printf("Error reading i2c boot information!\n");
  209. return 0; /* Don't want to hang() on this error */
  210. }
  211. val = (in & io_config) | (out & (~io_config));
  212. puts("rom_loc: ");
  213. if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
  214. puts("sd");
  215. #ifdef __SW_BOOT_SPI
  216. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
  217. puts("spi");
  218. #endif
  219. #ifdef __SW_BOOT_NAND
  220. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
  221. puts("nand");
  222. #endif
  223. #ifdef __SW_BOOT_PCIE
  224. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
  225. puts("pcie");
  226. #endif
  227. } else {
  228. if (val & 0x2)
  229. puts("nor lower bank");
  230. else
  231. puts("nor upper bank");
  232. }
  233. puts("\n");
  234. if (val & 0x1) {
  235. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  236. puts("SD/MMC : 8-bit Mode\n");
  237. puts("eSPI : Disabled\n");
  238. } else {
  239. puts("SD/MMC : 4-bit Mode\n");
  240. puts("eSPI : Enabled\n");
  241. }
  242. return 0;
  243. }
  244. #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
  245. void pci_init_board(void)
  246. {
  247. fsl_pcie_init_board(0);
  248. }
  249. #endif
  250. int board_early_init_r(void)
  251. {
  252. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  253. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  254. /*
  255. * Remap Boot flash region to caching-inhibited
  256. * so that flash can be erased properly.
  257. */
  258. /* Flush d-cache and invalidate i-cache of any FLASH data */
  259. flush_dcache();
  260. invalidate_icache();
  261. if (flash_esel == -1) {
  262. /* very unlikely unless something is messed up */
  263. puts("Error: Could not find TLB for FLASH BASE\n");
  264. flash_esel = 2; /* give our best effort to continue */
  265. } else {
  266. /* invalidate existing TLB entry for flash */
  267. disable_tlb(flash_esel);
  268. }
  269. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  270. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
  271. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  272. return 0;
  273. }
  274. int board_eth_init(bd_t *bis)
  275. {
  276. struct fsl_pq_mdio_info mdio_info;
  277. struct tsec_info_struct tsec_info[4];
  278. ccsr_gur_t *gur __attribute__((unused)) =
  279. (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  280. int num = 0;
  281. #ifdef CONFIG_VSC7385_ENET
  282. char *tmp;
  283. unsigned int vscfw_addr;
  284. #endif
  285. #ifdef CONFIG_TSEC1
  286. SET_STD_TSEC_INFO(tsec_info[num], 1);
  287. num++;
  288. #endif
  289. #ifdef CONFIG_TSEC2
  290. SET_STD_TSEC_INFO(tsec_info[num], 2);
  291. if (is_serdes_configured(SGMII_TSEC2)) {
  292. printf("eTSEC2 is in sgmii mode.\n");
  293. tsec_info[num].flags |= TSEC_SGMII;
  294. }
  295. num++;
  296. #endif
  297. #ifdef CONFIG_TSEC3
  298. SET_STD_TSEC_INFO(tsec_info[num], 3);
  299. num++;
  300. #endif
  301. if (!num) {
  302. printf("No TSECs initialized\n");
  303. return 0;
  304. }
  305. #ifdef CONFIG_VSC7385_ENET
  306. /* If a VSC7385 microcode image is present, then upload it. */
  307. tmp = env_get("vscfw_addr");
  308. if (tmp) {
  309. vscfw_addr = simple_strtoul(tmp, NULL, 16);
  310. printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
  311. if (vsc7385_upload_firmware((void *) vscfw_addr,
  312. CONFIG_VSC7385_IMAGE_SIZE))
  313. puts("Failure uploading VSC7385 microcode.\n");
  314. } else
  315. puts("No address specified for VSC7385 microcode.\n");
  316. #endif
  317. mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  318. mdio_info.name = DEFAULT_MII_NAME;
  319. fsl_pq_mdio_init(bis, &mdio_info);
  320. tsec_eth_init(bis, tsec_info, num);
  321. #if defined(CONFIG_UEC_ETH)
  322. /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
  323. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
  324. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
  325. uec_standard_init(bis);
  326. #endif
  327. return pci_eth_init(bis);
  328. }
  329. #if defined(CONFIG_QE) && \
  330. (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
  331. static void fdt_board_fixup_qe_pins(void *blob)
  332. {
  333. unsigned int oldbus;
  334. u8 val8;
  335. int node;
  336. fsl_lbc_t *lbc = LBC_BASE_ADDR;
  337. if (hwconfig("qe")) {
  338. /* For QE and eLBC pins multiplexing,
  339. * there is a PCA9555 device on P1025RDB.
  340. * It control the multiplex pins' functions,
  341. * and setting the PCA9555 can switch the
  342. * function between QE and eLBC.
  343. */
  344. oldbus = i2c_get_bus_num();
  345. i2c_set_bus_num(0);
  346. if (hwconfig("tdm"))
  347. val8 = PCA_IOPORT_QE_TDM_ENABLE;
  348. else
  349. val8 = PCA_IOPORT_QE_PIN_ENABLE;
  350. i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
  351. 1, &val8, 1);
  352. i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
  353. 1, &val8, 1);
  354. i2c_set_bus_num(oldbus);
  355. /* if run QE TDM, Set ABSWP to implement
  356. * conversion of addresses in the eLBC.
  357. */
  358. if (hwconfig("tdm")) {
  359. set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
  360. set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
  361. setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  362. }
  363. } else {
  364. node = fdt_path_offset(blob, "/qe");
  365. if (node >= 0)
  366. fdt_del_node(blob, node);
  367. }
  368. return;
  369. }
  370. #endif
  371. #ifdef CONFIG_OF_BOARD_SETUP
  372. int ft_board_setup(void *blob, bd_t *bd)
  373. {
  374. phys_addr_t base;
  375. phys_size_t size;
  376. #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
  377. const char *soc_usb_compat = "fsl-usb2-dr";
  378. int usb_err, usb1_off, usb2_off;
  379. #endif
  380. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  381. int err;
  382. #endif
  383. ft_cpu_setup(blob, bd);
  384. base = env_get_bootm_low();
  385. size = env_get_bootm_size();
  386. fdt_fixup_memory(blob, (u64)base, (u64)size);
  387. #if !defined(CONFIG_DM_PCI)
  388. FT_FSL_PCI_SETUP;
  389. #endif
  390. #ifdef CONFIG_QE
  391. do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
  392. sizeof("okay"), 0);
  393. #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
  394. fdt_board_fixup_qe_pins(blob);
  395. #endif
  396. #endif
  397. #if defined(CONFIG_HAS_FSL_DR_USB)
  398. fsl_fdt_fixup_dr_usb(blob, bd);
  399. #endif
  400. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  401. /* Delete eLBC node as it is muxed with USB2 controller */
  402. if (hwconfig("usb2")) {
  403. const char *soc_elbc_compat = "fsl,p1020-elbc";
  404. int off = fdt_node_offset_by_compatible(blob, -1,
  405. soc_elbc_compat);
  406. if (off < 0) {
  407. printf("WARNING: could not find compatible node %s\n",
  408. soc_elbc_compat);
  409. return off;
  410. }
  411. err = fdt_del_node(blob, off);
  412. if (err < 0) {
  413. printf("WARNING: could not remove %s\n",
  414. soc_elbc_compat);
  415. return err;
  416. }
  417. return 0;
  418. }
  419. #endif
  420. #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
  421. /* Delete USB2 node as it is muxed with eLBC */
  422. usb1_off = fdt_node_offset_by_compatible(blob, -1,
  423. soc_usb_compat);
  424. if (usb1_off < 0) {
  425. printf("WARNING: could not find compatible node %s\n",
  426. soc_usb_compat);
  427. return usb1_off;
  428. }
  429. usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
  430. soc_usb_compat);
  431. if (usb2_off < 0) {
  432. printf("WARNING: could not find compatible node %s\n",
  433. soc_usb_compat);
  434. return usb2_off;
  435. }
  436. usb_err = fdt_del_node(blob, usb2_off);
  437. if (usb_err < 0) {
  438. printf("WARNING: could not remove %s\n", soc_usb_compat);
  439. return usb_err;
  440. }
  441. #endif
  442. return 0;
  443. }
  444. #endif