spl.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <spl.h>
  9. #include <asm/io.h>
  10. #include <asm/mach-imx/iomux-v3.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx8mm_pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <asm/arch/ddr.h>
  16. #include <dm/uclass.h>
  17. #include <dm/device.h>
  18. #include <dm/uclass-internal.h>
  19. #include <dm/device-internal.h>
  20. #include <power/pmic.h>
  21. #include <power/bd71837.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int spl_board_boot_device(enum boot_device boot_dev_spl)
  24. {
  25. switch (boot_dev_spl) {
  26. case SD2_BOOT:
  27. case MMC2_BOOT:
  28. return BOOT_DEVICE_MMC1;
  29. case SD3_BOOT:
  30. case MMC3_BOOT:
  31. return BOOT_DEVICE_MMC2;
  32. default:
  33. return BOOT_DEVICE_NONE;
  34. }
  35. }
  36. void spl_dram_init(void)
  37. {
  38. ddr_init(&dram_timing);
  39. }
  40. void spl_board_init(void)
  41. {
  42. puts("Normal Boot\n");
  43. }
  44. #ifdef CONFIG_SPL_LOAD_FIT
  45. int board_fit_config_name_match(const char *name)
  46. {
  47. /* Just empty function now - can't decide what to choose */
  48. debug("%s: %s\n", __func__, name);
  49. return 0;
  50. }
  51. #endif
  52. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  53. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  54. static iomux_v3_cfg_t const uart_pads[] = {
  55. IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  56. IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  57. };
  58. static iomux_v3_cfg_t const wdog_pads[] = {
  59. IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  60. };
  61. int board_early_init_f(void)
  62. {
  63. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  64. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  65. set_wdog_reset(wdog);
  66. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  67. return 0;
  68. }
  69. int power_init_board(void)
  70. {
  71. struct udevice *dev;
  72. int ret;
  73. ret = pmic_get("pmic@4b", &dev);
  74. if (ret == -ENODEV) {
  75. puts("No pmic\n");
  76. return 0;
  77. }
  78. if (ret != 0)
  79. return ret;
  80. /* decrease RESET key long push time from the default 10s to 10ms */
  81. pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
  82. /* unlock the PMIC regs */
  83. pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
  84. /* increase VDD_SOC to typical value 0.85v before first DRAM access */
  85. pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
  86. /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
  87. pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
  88. #ifndef CONFIG_IMX8M_LPDDR4
  89. /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
  90. pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
  91. #endif
  92. /* lock the PMIC regs */
  93. pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
  94. return 0;
  95. }
  96. void board_init_f(ulong dummy)
  97. {
  98. struct udevice *dev;
  99. int ret;
  100. arch_cpu_init();
  101. init_uart_clk(1);
  102. board_early_init_f();
  103. timer_init();
  104. preloader_console_init();
  105. /* Clear the BSS. */
  106. memset(__bss_start, 0, __bss_end - __bss_start);
  107. ret = spl_early_init();
  108. if (ret) {
  109. debug("spl_early_init() failed: %d\n", ret);
  110. hang();
  111. }
  112. ret = uclass_get_device_by_name(UCLASS_CLK,
  113. "clock-controller@30380000",
  114. &dev);
  115. if (ret < 0) {
  116. printf("Failed to find clock node. Check device tree\n");
  117. hang();
  118. }
  119. enable_tzc380();
  120. power_init_board();
  121. /* DDR initialization */
  122. spl_dram_init();
  123. board_init_r(NULL, 0);
  124. }
  125. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  126. {
  127. puts ("resetting ...\n");
  128. reset_cpu(WDOG1_BASE_ADDR);
  129. return 0;
  130. }