spl.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Compulab, Ltd.
  4. */
  5. #include <common.h>
  6. #include <hang.h>
  7. #include <init.h>
  8. #include <spl.h>
  9. #include <i2c.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/ddr_defs.h>
  12. #include <asm/gpio.h>
  13. #include <power/pmic.h>
  14. #include <power/tps65218.h>
  15. #include "board.h"
  16. const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
  17. const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
  18. const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
  19. const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
  20. const struct ctrl_ioregs ioregs_ddr3 = {
  21. .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
  22. .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
  23. .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
  24. .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
  25. .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
  26. .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  27. .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
  28. .emif_sdram_config_ext = 0x0143,
  29. };
  30. /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
  31. struct emif_regs ddr3_emif_regs = {
  32. .sdram_config = 0x638413B2,
  33. .ref_ctrl = 0x00000C30,
  34. .sdram_tim1 = 0xEAAAD4DB,
  35. .sdram_tim2 = 0x266B7FDA,
  36. .sdram_tim3 = 0x107F8678,
  37. .read_idle_ctrl = 0x00050000,
  38. .zq_config = 0x50074BE4,
  39. .temp_alert_config = 0x0,
  40. .emif_ddr_phy_ctlr_1 = 0x0E004008,
  41. .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
  42. .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
  43. .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
  44. .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
  45. .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
  46. .emif_rd_wr_exec_thresh = 0x80000405,
  47. .emif_prio_class_serv_map = 0x80000001,
  48. .emif_connect_id_serv_1_map = 0x80000094,
  49. .emif_connect_id_serv_2_map = 0x00000000,
  50. .emif_cos_config = 0x000FFFFF
  51. };
  52. const u32 ext_phy_ctrl_const_base_ddr3[] = {
  53. 0x00000000,
  54. 0x00000044,
  55. 0x00000044,
  56. 0x00000046,
  57. 0x00000046,
  58. 0x00000000,
  59. 0x00000059,
  60. 0x00000077,
  61. 0x00000093,
  62. 0x000000A8,
  63. 0x00000000,
  64. 0x00000019,
  65. 0x00000037,
  66. 0x00000053,
  67. 0x00000068,
  68. 0x00000000,
  69. 0x0,
  70. 0x0,
  71. 0x40000000,
  72. 0x08102040
  73. };
  74. void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
  75. {
  76. *regs = ext_phy_ctrl_const_base_ddr3;
  77. *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
  78. }
  79. const struct dpll_params *get_dpll_ddr_params(void)
  80. {
  81. return &dpll_ddr;
  82. }
  83. const struct dpll_params *get_dpll_mpu_params(void)
  84. {
  85. return &dpll_mpu;
  86. }
  87. const struct dpll_params *get_dpll_core_params(void)
  88. {
  89. return &dpll_core;
  90. }
  91. const struct dpll_params *get_dpll_per_params(void)
  92. {
  93. return &dpll_per;
  94. }
  95. void scale_vcores(void)
  96. {
  97. set_i2c_pin_mux();
  98. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  99. if (i2c_probe(TPS65218_CHIP_PM))
  100. return;
  101. tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV);
  102. tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV);
  103. }
  104. void sdram_init(void)
  105. {
  106. unsigned long ram_size;
  107. config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
  108. ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  109. if (ram_size == 0x80000000 ||
  110. ram_size == 0x40000000 ||
  111. ram_size == 0x20000000)
  112. return;
  113. ddr3_emif_regs.sdram_config = 0x638453B2;
  114. config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
  115. ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
  116. if (ram_size == 0x08000000)
  117. return;
  118. hang();
  119. }