mux.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * (C) Copyright 2016
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  10. */
  11. #include <common.h>
  12. #include <hang.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/mux.h>
  16. #include <asm/io.h>
  17. #include <i2c.h>
  18. #include "board.h"
  19. static struct module_pin_mux uart0_pin_mux[] = {
  20. {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
  21. {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
  22. {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
  23. {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
  24. {-1},
  25. };
  26. static struct module_pin_mux uart1_pin_mux[] = {
  27. {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
  28. {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
  29. {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
  30. {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
  31. {-1},
  32. };
  33. static struct module_pin_mux uart2_pin_mux[] = {
  34. {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
  35. {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
  36. {-1},
  37. };
  38. static struct module_pin_mux spi1_pin_mux[] = {
  39. {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */
  40. {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */
  41. {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */
  42. {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */
  43. {-1},
  44. };
  45. static struct module_pin_mux uart4_pin_mux[] = {
  46. {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
  47. {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */
  48. {-1},
  49. };
  50. static struct module_pin_mux mmc0_pin_mux[] = {
  51. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */
  52. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */
  53. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */
  54. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */
  55. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  56. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */
  57. {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */
  58. {-1},
  59. };
  60. static struct module_pin_mux mmc1_pin_mux[] = {
  61. {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  62. {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  63. {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  64. {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  65. {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  66. {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  67. {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  68. {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  69. {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */
  70. {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  71. {-1},
  72. };
  73. static struct module_pin_mux mmc2_pin_mux[] = {
  74. {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */
  75. {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */
  76. {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */
  77. {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */
  78. {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */
  79. {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */
  80. {-1},
  81. };
  82. static struct module_pin_mux i2c0_pin_mux[] = {
  83. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */
  84. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */
  85. {-1},
  86. };
  87. static struct module_pin_mux gpio0_7_pin_mux[] = {
  88. {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */
  89. {-1},
  90. };
  91. static struct module_pin_mux jtag_pin_mux[] = {
  92. {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)},
  93. {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)},
  94. {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
  95. {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
  96. {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
  97. {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
  98. {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
  99. {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
  100. {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
  101. {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
  102. {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
  103. {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
  104. {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
  105. {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
  106. {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
  107. {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
  108. {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)},
  109. {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)},
  110. {-1},
  111. };
  112. static struct module_pin_mux gpio_pin_mux[] = {
  113. {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */
  114. {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */
  115. {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */
  116. {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */
  117. {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */
  118. {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */
  119. {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */
  120. {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */
  121. {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */
  122. {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */
  123. {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */
  124. {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */
  125. {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */
  126. {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */
  127. {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */
  128. {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */
  129. {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */
  130. {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */
  131. {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */
  132. {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */
  133. {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */
  134. {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */
  135. {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */
  136. {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */
  137. {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */
  138. {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */
  139. {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */
  140. {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */
  141. {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */
  142. {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */
  143. {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */
  144. {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */
  145. {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */
  146. {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */
  147. {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */
  148. {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */
  149. {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */
  150. {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */
  151. {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */
  152. {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */
  153. {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */
  154. {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */
  155. {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */
  156. {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */
  157. {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */
  158. {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */
  159. {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */
  160. {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */
  161. {-1},
  162. };
  163. static struct module_pin_mux mii1_pin_mux[] = {
  164. {OFFSET(mii1_col), MODE(0) | RXACTIVE},
  165. {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
  166. {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
  167. {OFFSET(mii1_txen), MODE(0)},
  168. {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
  169. {OFFSET(mii1_txd3), MODE(0)},
  170. {OFFSET(mii1_txd2), MODE(0)},
  171. {OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
  172. {OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
  173. {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
  174. {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
  175. {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
  176. {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
  177. {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
  178. {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
  179. {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},
  180. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
  181. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
  182. {-1},
  183. };
  184. static struct module_pin_mux pwm_pin_mux[] = {
  185. {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)},
  186. {-1},
  187. };
  188. void enable_uart0_pin_mux(void)
  189. {
  190. configure_module_pin_mux(uart0_pin_mux);
  191. }
  192. void enable_uart1_pin_mux(void)
  193. {
  194. configure_module_pin_mux(uart1_pin_mux);
  195. }
  196. void enable_uart2_pin_mux(void)
  197. {
  198. configure_module_pin_mux(uart2_pin_mux);
  199. }
  200. void enable_uart3_pin_mux(void)
  201. {
  202. }
  203. void enable_uart4_pin_mux(void)
  204. {
  205. configure_module_pin_mux(uart4_pin_mux);
  206. }
  207. void enable_uart5_pin_mux(void)
  208. {
  209. }
  210. void enable_i2c0_pin_mux(void)
  211. {
  212. configure_module_pin_mux(i2c0_pin_mux);
  213. }
  214. void enable_shc_board_pwm_pin_mux(void)
  215. {
  216. configure_module_pin_mux(pwm_pin_mux);
  217. }
  218. void enable_shc_board_pin_mux(void)
  219. {
  220. /* Do board-specific muxes. */
  221. if (board_is_c3_sample() || board_is_series()) {
  222. configure_module_pin_mux(mii1_pin_mux);
  223. configure_module_pin_mux(mmc0_pin_mux);
  224. configure_module_pin_mux(mmc1_pin_mux);
  225. configure_module_pin_mux(mmc2_pin_mux);
  226. configure_module_pin_mux(i2c0_pin_mux);
  227. configure_module_pin_mux(gpio0_7_pin_mux);
  228. configure_module_pin_mux(gpio_pin_mux);
  229. configure_module_pin_mux(uart1_pin_mux);
  230. configure_module_pin_mux(uart2_pin_mux);
  231. configure_module_pin_mux(uart4_pin_mux);
  232. configure_module_pin_mux(spi1_pin_mux);
  233. configure_module_pin_mux(jtag_pin_mux);
  234. } else {
  235. puts("Unknown board, cannot configure pinmux.");
  236. hang();
  237. }
  238. }