tpl.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <debug_uart.h>
  7. #include <dm.h>
  8. #include <hang.h>
  9. #include <spl.h>
  10. #include <asm/cpu.h>
  11. #include <asm/mtrr.h>
  12. #include <asm/processor.h>
  13. #include <asm-generic/sections.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. __weak int arch_cpu_init_dm(void)
  16. {
  17. return 0;
  18. }
  19. static int x86_tpl_init(void)
  20. {
  21. int ret;
  22. debug("%s starting\n", __func__);
  23. ret = x86_cpu_init_tpl();
  24. if (ret) {
  25. debug("%s: x86_cpu_init_tpl() failed\n", __func__);
  26. return ret;
  27. }
  28. ret = spl_init();
  29. if (ret) {
  30. debug("%s: spl_init() failed\n", __func__);
  31. return ret;
  32. }
  33. ret = arch_cpu_init();
  34. if (ret) {
  35. debug("%s: arch_cpu_init() failed\n", __func__);
  36. return ret;
  37. }
  38. ret = arch_cpu_init_dm();
  39. if (ret) {
  40. debug("%s: arch_cpu_init_dm() failed\n", __func__);
  41. return ret;
  42. }
  43. preloader_console_init();
  44. return 0;
  45. }
  46. void board_init_f(ulong flags)
  47. {
  48. int ret;
  49. ret = x86_tpl_init();
  50. if (ret) {
  51. debug("Error %d\n", ret);
  52. panic("x86_tpl_init fail");
  53. }
  54. /* Uninit CAR and jump to board_init_f_r() */
  55. board_init_r(gd, 0);
  56. }
  57. void board_init_f_r(void)
  58. {
  59. /* Not used since we never call board_init_f_r_trampoline() */
  60. while (1);
  61. }
  62. u32 spl_boot_device(void)
  63. {
  64. return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
  65. BOOT_DEVICE_SPI_MMAP;
  66. }
  67. int spl_start_uboot(void)
  68. {
  69. return 0;
  70. }
  71. void spl_board_announce_boot_device(void)
  72. {
  73. printf("SPI flash");
  74. }
  75. static int spl_board_load_image(struct spl_image_info *spl_image,
  76. struct spl_boot_device *bootdev)
  77. {
  78. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  79. spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
  80. spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
  81. spl_image->os = IH_OS_U_BOOT;
  82. spl_image->name = "U-Boot";
  83. debug("Loading to %lx\n", spl_image->load_addr);
  84. return 0;
  85. }
  86. SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
  87. int spl_spi_load_image(void)
  88. {
  89. return -EPERM;
  90. }
  91. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  92. {
  93. debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
  94. jump_to_spl(spl_image->entry_point);
  95. hang();
  96. }
  97. void spl_board_init(void)
  98. {
  99. preloader_console_init();
  100. }
  101. #if !CONFIG_IS_ENABLED(PCI)
  102. /*
  103. * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
  104. * to bind the devices on the PCI bus, some of which have early-regs properties
  105. * providing fixed BARs. Individual drivers program these BARs themselves so
  106. * that they can access the devices. The BARs are allocated statically in the
  107. * device tree.
  108. *
  109. * Once SPL is running it enables PCI properly, but does not auto-assign BARs
  110. * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
  111. * the auto allocation (after relocation).
  112. */
  113. static const struct udevice_id tpl_fake_pci_ids[] = {
  114. { .compatible = "pci-x86" },
  115. { }
  116. };
  117. U_BOOT_DRIVER(pci_x86) = {
  118. .name = "pci_x86",
  119. .id = UCLASS_SIMPLE_BUS,
  120. .of_match = tpl_fake_pci_ids,
  121. };
  122. #endif