sdram.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * JZ4780 DDR initialization
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. *
  8. * Based on spl/common/{jz4780_ddr,jz_ddr3_init}.c from X-Boot
  9. * Copyright (c) 2006-2013 Ingenic Semiconductor
  10. */
  11. #include <common.h>
  12. #include <hang.h>
  13. #include <asm/io.h>
  14. #include <mach/jz4780.h>
  15. #include <mach/jz4780_dram.h>
  16. static const u32 get_mem_clk(void)
  17. {
  18. const u32 mpll_out = ((u64)JZ4780_SYS_EXTAL * JZ4780_MPLL_M) /
  19. (JZ4780_MPLL_N * JZ4780_MPLL_OD);
  20. return mpll_out / JZ4780_SYS_MEM_DIV;
  21. }
  22. u32 sdram_size(int cs)
  23. {
  24. u32 dw = DDR_DW32 ? 4 : 2;
  25. u32 banks = DDR_BANK8 ? 8 : 4;
  26. u32 size = 0;
  27. if ((cs == 0) && DDR_CS0EN) {
  28. size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
  29. if (DDR_CS1EN && (size > 0x20000000))
  30. size = 0x20000000;
  31. } else if ((cs == 1) && DDR_CS1EN) {
  32. size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
  33. }
  34. return size;
  35. }
  36. static void ddr_cfg_init(void)
  37. {
  38. void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
  39. u32 ddrc_cfg, tmp;
  40. tmp = DDR_CL;
  41. if (tmp)
  42. tmp--;
  43. if (tmp > 4)
  44. tmp = 4;
  45. ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA |
  46. DDR_DW32 | DDRC_CFG_MPRT | ((tmp | 0x8) << 2) |
  47. ((DDR_ROW - 12) << 11) | ((DDR_COL - 8) << 8) |
  48. (DDR_CS0EN << 6) | (DDR_BANK8 << 1) |
  49. ((DDR_ROW - 12) << 27) | ((DDR_COL - 8) << 24) |
  50. (DDR_CS1EN << 7) | (DDR_BANK8 << 23);
  51. if (DDR_BL > 4)
  52. ddrc_cfg |= BIT(21);
  53. writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG);
  54. }
  55. static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config)
  56. {
  57. void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
  58. void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
  59. unsigned int count = 0, i;
  60. u32 reg, mask;
  61. writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), ddr_phy_regs + DDRP_DCR);
  62. writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0);
  63. writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1);
  64. writel(0, ddr_phy_regs + DDRP_ODTCR);
  65. writel(0, ddr_phy_regs + DDRP_MR2);
  66. writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0);
  67. writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1);
  68. writel(ddr_config->ptr2, ddr_phy_regs + DDRP_PTR2);
  69. writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0);
  70. writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1);
  71. writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2);
  72. writel(DDRP_PGCR_DQSCFG | (7 << DDRP_PGCR_CKEN_BIT) |
  73. (2 << DDRP_PGCR_CKDV_BIT) |
  74. (DDR_CS0EN | (DDR_CS1EN << 1)) << DDRP_PGCR_RANKEN_BIT |
  75. DDRP_PGCR_ZCKSEL_32 | DDRP_PGCR_PDDISDX,
  76. ddr_phy_regs + DDRP_PGCR);
  77. for (i = 0; i < 8; i++)
  78. clrbits_le32(ddr_phy_regs + DDRP_DXGCR(i), 0x3 << 9);
  79. count = 0;
  80. mask = DDRP_PGSR_IDONE | DDRP_PGSR_DLDONE | DDRP_PGSR_ZCDONE;
  81. for (;;) {
  82. reg = readl(ddr_phy_regs + DDRP_PGSR);
  83. if ((reg == mask) || (reg == 0x1f))
  84. break;
  85. if (count++ == 10000)
  86. hang();
  87. }
  88. /* DQS extension and early set to 1 */
  89. clrsetbits_le32(ddr_phy_regs + DDRP_DSGCR, 0x7E << 4, 0x12 << 4);
  90. /* 500 pull up and 500 pull down */
  91. clrsetbits_le32(ddr_phy_regs + DDRP_DXCCR, 0xFF << 4, 0xC4 << 4);
  92. /* Initialise phy */
  93. writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST,
  94. ddr_phy_regs + DDRP_PIR);
  95. count = 0;
  96. mask |= DDRP_PGSR_DIDONE;
  97. for (;;) {
  98. reg = readl(ddr_phy_regs + DDRP_PGSR);
  99. if ((reg == mask) || (reg == 0x1f))
  100. break;
  101. if (count++ == 20000)
  102. hang();
  103. }
  104. writel(DDRP_PIR_INIT | DDRP_PIR_QSTRN, ddr_phy_regs + DDRP_PIR);
  105. count = 0;
  106. mask |= DDRP_PGSR_DTDONE;
  107. for (;;) {
  108. reg = readl(ddr_phy_regs + DDRP_PGSR);
  109. if (reg == mask)
  110. break;
  111. if (count++ != 50000)
  112. continue;
  113. reg &= DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR;
  114. if (reg)
  115. hang();
  116. count = 0;
  117. }
  118. /* Override impedance */
  119. clrsetbits_le32(ddr_phy_regs + DDRP_ZQXCR0(0), 0x3ff,
  120. ((ddr_config->pullup & 0x1f) << DDRP_ZQXCR_PULLUP_IMPE_BIT) |
  121. ((ddr_config->pulldn & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPE_BIT) |
  122. DDRP_ZQXCR_ZDEN);
  123. }
  124. #define JZBIT(bit) ((bit % 4) * 8)
  125. #define JZMASK(bit) (0x1f << JZBIT(bit))
  126. static void remap_swap(int a, int b)
  127. {
  128. void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
  129. u32 remmap[2], tmp[2];
  130. remmap[0] = readl(ddr_ctl_regs + DDRC_REMMAP(a / 4));
  131. remmap[1] = readl(ddr_ctl_regs + DDRC_REMMAP(b / 4));
  132. tmp[0] = (remmap[0] & JZMASK(a)) >> JZBIT(a);
  133. tmp[1] = (remmap[1] & JZMASK(b)) >> JZBIT(b);
  134. remmap[0] &= ~JZMASK(a);
  135. remmap[1] &= ~JZMASK(b);
  136. writel(remmap[0] | (tmp[1] << JZBIT(a)),
  137. ddr_ctl_regs + DDRC_REMMAP(a / 4));
  138. writel(remmap[1] | (tmp[0] << JZBIT(b)),
  139. ddr_ctl_regs + DDRC_REMMAP(b / 4));
  140. }
  141. static void mem_remap(void)
  142. {
  143. u32 start = (DDR_ROW + DDR_COL + (DDR_DW32 ? 4 : 2) / 2) - 12;
  144. u32 num = DDR_BANK8 ? 3 : 2;
  145. if (DDR_CS0EN && DDR_CS1EN)
  146. num++;
  147. for (; num > 0; num--)
  148. remap_swap(0 + num - 1, start + num - 1);
  149. }
  150. /* Fetch DRAM config from board file */
  151. __weak const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
  152. {
  153. return NULL;
  154. }
  155. void sdram_init(void)
  156. {
  157. const struct jz4780_ddr_config *ddr_config = jz4780_get_ddr_config();
  158. void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
  159. void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
  160. void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
  161. u32 mem_clk, tmp, i;
  162. u32 mem_base0, mem_base1;
  163. u32 mem_mask0, mem_mask1;
  164. u32 mem_size0, mem_size1;
  165. if (!ddr_config)
  166. hang();
  167. /* Reset DLL in DDR PHY */
  168. writel(0x3, cpm_regs + 0xd0);
  169. mdelay(400);
  170. writel(0x1, cpm_regs + 0xd0);
  171. mdelay(400);
  172. /* Enter reset */
  173. writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL);
  174. mem_clk = get_mem_clk();
  175. tmp = 1000000000 / mem_clk;
  176. if (1000000000 % mem_clk)
  177. tmp++;
  178. tmp = DDR_tREFI / tmp;
  179. tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1;
  180. if (tmp > 0xff)
  181. tmp = 0xff;
  182. if (tmp < 1)
  183. tmp = 1;
  184. writel(0x0, ddr_ctl_regs + DDRC_CTRL);
  185. writel(0x150000, ddr_phy_regs + DDRP_DTAR);
  186. ddr_phy_init(ddr_config);
  187. writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
  188. writel(0x0, ddr_ctl_regs + DDRC_CTRL);
  189. ddr_cfg_init();
  190. for (i = 0; i < 6; i++)
  191. writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i));
  192. mem_size0 = sdram_size(0);
  193. mem_size1 = sdram_size(1);
  194. if (!mem_size1 && mem_size0 > 0x20000000) {
  195. mem_base0 = 0x0;
  196. mem_mask0 = ~(((mem_size0 * 2) >> 24) - 1) & DDRC_MMAP_MASK_MASK;
  197. } else {
  198. mem_base0 = (DDR_MEM_PHY_BASE >> 24) & 0xff;
  199. mem_mask0 = ~((mem_size0 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
  200. }
  201. if (mem_size1) {
  202. mem_mask1 = ~((mem_size1 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
  203. mem_base1 = ((DDR_MEM_PHY_BASE + mem_size0) >> 24) & 0xff;
  204. } else {
  205. mem_mask1 = 0;
  206. mem_base1 = 0xff;
  207. }
  208. writel(mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0,
  209. ddr_ctl_regs + DDRC_MMAP0);
  210. writel(mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1,
  211. ddr_ctl_regs + DDRC_MMAP1);
  212. writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
  213. writel((DDR_CLK_DIV << 1) | DDRC_REFCNT_REF_EN |
  214. (tmp << DDRC_REFCNT_CON_BIT),
  215. ddr_ctl_regs + DDRC_REFCNT);
  216. writel((1 << 15) | (4 << 12) | (1 << 11) | (1 << 8) | (0 << 6) |
  217. (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1),
  218. ddr_ctl_regs + DDRC_CTRL);
  219. mem_remap();
  220. clrbits_le32(ddr_ctl_regs + DDRC_ST, 0x40);
  221. }