spl_s10.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <hang.h>
  7. #include <asm/io.h>
  8. #include <asm/u-boot.h>
  9. #include <asm/utils.h>
  10. #include <common.h>
  11. #include <debug_uart.h>
  12. #include <image.h>
  13. #include <spl.h>
  14. #include <asm/arch/clock_manager.h>
  15. #include <asm/arch/firewall.h>
  16. #include <asm/arch/mailbox_s10.h>
  17. #include <asm/arch/misc.h>
  18. #include <asm/arch/reset_manager.h>
  19. #include <asm/arch/system_manager.h>
  20. #include <watchdog.h>
  21. #include <dm/uclass.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. u32 spl_boot_device(void)
  24. {
  25. /* TODO: Get from SDM or handoff */
  26. return BOOT_DEVICE_MMC1;
  27. }
  28. #ifdef CONFIG_SPL_MMC_SUPPORT
  29. u32 spl_boot_mode(const u32 boot_device)
  30. {
  31. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  32. return MMCSD_MODE_FS;
  33. #else
  34. return MMCSD_MODE_RAW;
  35. #endif
  36. }
  37. #endif
  38. void board_init_f(ulong dummy)
  39. {
  40. const struct cm_config *cm_default_cfg = cm_get_default_config();
  41. int ret;
  42. ret = spl_early_init();
  43. if (ret)
  44. hang();
  45. socfpga_get_managers_addr();
  46. #ifdef CONFIG_HW_WATCHDOG
  47. /* Ensure watchdog is paused when debugging is happening */
  48. writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  49. socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  50. /* Enable watchdog before initializing the HW */
  51. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  52. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  53. hw_watchdog_init();
  54. #endif
  55. /* ensure all processors are not released prior Linux boot */
  56. writeq(0, CPU_RELEASE_ADDR);
  57. socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  58. timer_init();
  59. sysmgr_pinmux_init();
  60. /* configuring the HPS clocks */
  61. cm_basic_init(cm_default_cfg);
  62. #ifdef CONFIG_DEBUG_UART
  63. socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  64. debug_uart_init();
  65. #endif
  66. preloader_console_init();
  67. cm_print_clock_quick_summary();
  68. firewall_setup();
  69. /* disable ocram security at CCU for non secure access */
  70. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
  71. CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  72. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
  73. CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  74. #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  75. struct udevice *dev;
  76. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  77. if (ret) {
  78. debug("DRAM init failed: %d\n", ret);
  79. hang();
  80. }
  81. #endif
  82. mbox_init();
  83. #ifdef CONFIG_CADENCE_QSPI
  84. mbox_qspi_open();
  85. #endif
  86. }