spl_a10.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <asm/io.h>
  9. #include <asm/pl310.h>
  10. #include <asm/u-boot.h>
  11. #include <asm/utils.h>
  12. #include <image.h>
  13. #include <asm/arch/reset_manager.h>
  14. #include <spl.h>
  15. #include <asm/arch/system_manager.h>
  16. #include <asm/arch/freeze_controller.h>
  17. #include <asm/arch/clock_manager.h>
  18. #include <asm/arch/scan_manager.h>
  19. #include <asm/arch/sdram.h>
  20. #include <asm/arch/scu.h>
  21. #include <asm/arch/misc.h>
  22. #include <asm/arch/nic301.h>
  23. #include <asm/sections.h>
  24. #include <fdtdec.h>
  25. #include <watchdog.h>
  26. #include <asm/arch/pinmux.h>
  27. #include <asm/arch/fpga_manager.h>
  28. #include <mmc.h>
  29. #include <memalign.h>
  30. #define FPGA_BUFSIZ 16 * 1024
  31. DECLARE_GLOBAL_DATA_PTR;
  32. u32 spl_boot_device(void)
  33. {
  34. const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
  35. switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
  36. case 0x1: /* FPGA (HPS2FPGA Bridge) */
  37. return BOOT_DEVICE_RAM;
  38. case 0x2: /* NAND Flash (1.8V) */
  39. case 0x3: /* NAND Flash (3.0V) */
  40. socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
  41. return BOOT_DEVICE_NAND;
  42. case 0x4: /* SD/MMC External Transceiver (1.8V) */
  43. case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
  44. socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  45. socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  46. return BOOT_DEVICE_MMC1;
  47. case 0x6: /* QSPI Flash (1.8V) */
  48. case 0x7: /* QSPI Flash (3.0V) */
  49. socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  50. return BOOT_DEVICE_SPI;
  51. default:
  52. printf("Invalid boot device (bsel=%08x)!\n", bsel);
  53. hang();
  54. }
  55. }
  56. #ifdef CONFIG_SPL_MMC_SUPPORT
  57. u32 spl_boot_mode(const u32 boot_device)
  58. {
  59. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  60. return MMCSD_MODE_FS;
  61. #else
  62. return MMCSD_MODE_RAW;
  63. #endif
  64. }
  65. #endif
  66. void spl_board_init(void)
  67. {
  68. ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
  69. /* enable console uart printing */
  70. preloader_console_init();
  71. WATCHDOG_RESET();
  72. arch_early_init_r();
  73. /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
  74. if (is_fpgamgr_user_mode()) {
  75. int ret = config_pins(gd->fdt_blob, "shared");
  76. if (ret)
  77. return;
  78. ret = config_pins(gd->fdt_blob, "fpga");
  79. if (ret)
  80. return;
  81. } else if (!is_fpgamgr_early_user_mode()) {
  82. /* Program IOSSM(early IO release) or full FPGA */
  83. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  84. }
  85. /* If the IOSSM/full FPGA is already loaded, start DDR */
  86. if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
  87. ddr_calibration_sequence();
  88. if (!is_fpgamgr_user_mode())
  89. fpgamgr_program(buf, FPGA_BUFSIZ, 0);
  90. }
  91. void board_init_f(ulong dummy)
  92. {
  93. if (spl_early_init())
  94. hang();
  95. socfpga_get_managers_addr();
  96. dcache_disable();
  97. socfpga_init_security_policies();
  98. socfpga_sdram_remap_zero();
  99. socfpga_pl310_clear();
  100. /* Assert reset to all except L4WD0 and L4TIMER0 */
  101. socfpga_per_reset_all();
  102. socfpga_watchdog_disable();
  103. /* Configure the clock based on handoff */
  104. cm_basic_init(gd->fdt_blob);
  105. #ifdef CONFIG_HW_WATCHDOG
  106. /* release osc1 watchdog timer 0 from reset */
  107. socfpga_reset_deassert_osc1wd0();
  108. /* reconfigure and enable the watchdog */
  109. hw_watchdog_init();
  110. WATCHDOG_RESET();
  111. #endif /* CONFIG_HW_WATCHDOG */
  112. config_dedicated_pins(gd->fdt_blob);
  113. WATCHDOG_RESET();
  114. }