misc.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <asm/io.h>
  9. #include <errno.h>
  10. #include <fdtdec.h>
  11. #include <linux/libfdt.h>
  12. #include <altera.h>
  13. #include <miiphy.h>
  14. #include <netdev.h>
  15. #include <watchdog.h>
  16. #include <asm/arch/misc.h>
  17. #include <asm/arch/reset_manager.h>
  18. #include <asm/arch/scan_manager.h>
  19. #include <asm/arch/system_manager.h>
  20. #include <asm/arch/nic301.h>
  21. #include <asm/arch/scu.h>
  22. #include <asm/pl310.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. phys_addr_t socfpga_clkmgr_base __section(".data");
  25. phys_addr_t socfpga_rstmgr_base __section(".data");
  26. phys_addr_t socfpga_sysmgr_base __section(".data");
  27. #ifdef CONFIG_SYS_L2_PL310
  28. static const struct pl310_regs *const pl310 =
  29. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30. #endif
  31. struct bsel bsel_str[] = {
  32. { "rsvd", "Reserved", },
  33. { "fpga", "FPGA (HPS2FPGA Bridge)", },
  34. { "nand", "NAND Flash (1.8V)", },
  35. { "nand", "NAND Flash (3.0V)", },
  36. { "sd", "SD/MMC External Transceiver (1.8V)", },
  37. { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  38. { "qspi", "QSPI Flash (1.8V)", },
  39. { "qspi", "QSPI Flash (3.0V)", },
  40. };
  41. int dram_init(void)
  42. {
  43. if (fdtdec_setup_mem_size_base() != 0)
  44. return -EINVAL;
  45. return 0;
  46. }
  47. void enable_caches(void)
  48. {
  49. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  50. icache_enable();
  51. #endif
  52. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  53. dcache_enable();
  54. #endif
  55. }
  56. #ifdef CONFIG_SYS_L2_PL310
  57. void v7_outer_cache_enable(void)
  58. {
  59. struct udevice *dev;
  60. if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  61. pr_err("cache controller driver NOT found!\n");
  62. }
  63. void v7_outer_cache_disable(void)
  64. {
  65. /* Disable the L2 cache */
  66. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  67. }
  68. void socfpga_pl310_clear(void)
  69. {
  70. u32 mask = 0xff, ena = 0;
  71. icache_enable();
  72. /* Disable the L2 cache */
  73. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  74. writel(0x0, &pl310->pl310_tag_latency_ctrl);
  75. writel(0x10, &pl310->pl310_data_latency_ctrl);
  76. /* enable BRESP, instruction and data prefetch, full line of zeroes */
  77. setbits_le32(&pl310->pl310_aux_ctrl,
  78. L310_AUX_CTRL_DATA_PREFETCH_MASK |
  79. L310_AUX_CTRL_INST_PREFETCH_MASK |
  80. L310_SHARED_ATT_OVERRIDE_ENABLE);
  81. /* Enable the L2 cache */
  82. ena = readl(&pl310->pl310_ctrl);
  83. ena |= L2X0_CTRL_EN;
  84. /*
  85. * Invalidate the PL310 L2 cache. Keep the invalidation code
  86. * entirely in L1 I-cache to avoid any bus traffic through
  87. * the L2.
  88. */
  89. asm volatile(
  90. ".align 5 \n"
  91. " b 3f \n"
  92. "1: str %1, [%4] \n"
  93. " dsb \n"
  94. " isb \n"
  95. " str %0, [%2] \n"
  96. " dsb \n"
  97. " isb \n"
  98. "2: ldr %0, [%2] \n"
  99. " cmp %0, #0 \n"
  100. " bne 2b \n"
  101. " str %0, [%3] \n"
  102. " dsb \n"
  103. " isb \n"
  104. " b 4f \n"
  105. "3: b 1b \n"
  106. "4: nop \n"
  107. : "+r"(mask), "+r"(ena)
  108. : "r"(&pl310->pl310_inv_way),
  109. "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
  110. : "memory", "cc");
  111. /* Disable the L2 cache */
  112. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  113. }
  114. #endif
  115. #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  116. defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  117. int overwrite_console(void)
  118. {
  119. return 0;
  120. }
  121. #endif
  122. #ifdef CONFIG_FPGA
  123. /* add device descriptor to FPGA device table */
  124. void socfpga_fpga_add(void *fpga_desc)
  125. {
  126. fpga_init();
  127. fpga_add(fpga_altera, fpga_desc);
  128. }
  129. #endif
  130. int arch_cpu_init(void)
  131. {
  132. socfpga_get_managers_addr();
  133. #ifdef CONFIG_HW_WATCHDOG
  134. /*
  135. * In case the watchdog is enabled, make sure to (re-)configure it
  136. * so that the defined timeout is valid. Otherwise the SPL (Perloader)
  137. * timeout value is still active which might too short for Linux
  138. * booting.
  139. */
  140. hw_watchdog_init();
  141. #else
  142. /*
  143. * If the HW watchdog is NOT enabled, make sure it is not running,
  144. * for example because it was enabled in the preloader. This might
  145. * trigger a watchdog-triggered reboot of Linux kernel later.
  146. * Toggle watchdog reset, so watchdog in not running state.
  147. */
  148. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  149. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  150. #endif
  151. return 0;
  152. }
  153. #ifndef CONFIG_SPL_BUILD
  154. static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  155. {
  156. unsigned int mask = ~0;
  157. if (argc < 2 || argc > 3)
  158. return CMD_RET_USAGE;
  159. argv++;
  160. if (argc == 3)
  161. mask = simple_strtoul(argv[1], NULL, 16);
  162. switch (*argv[0]) {
  163. case 'e': /* Enable */
  164. do_bridge_reset(1, mask);
  165. break;
  166. case 'd': /* Disable */
  167. do_bridge_reset(0, mask);
  168. break;
  169. default:
  170. return CMD_RET_USAGE;
  171. }
  172. return 0;
  173. }
  174. U_BOOT_CMD(bridge, 3, 1, do_bridge,
  175. "SoCFPGA HPS FPGA bridge control",
  176. "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  177. "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  178. ""
  179. );
  180. #endif
  181. static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
  182. {
  183. const void *blob = gd->fdt_blob;
  184. struct fdt_resource r;
  185. int node;
  186. int ret;
  187. node = fdt_node_offset_by_compatible(blob, -1, compat);
  188. if (node < 0)
  189. return node;
  190. if (!fdtdec_get_is_enabled(blob, node))
  191. return -ENODEV;
  192. ret = fdt_get_resource(blob, node, "reg", 0, &r);
  193. if (ret)
  194. return ret;
  195. *base = (phys_addr_t)r.start;
  196. return 0;
  197. }
  198. void socfpga_get_managers_addr(void)
  199. {
  200. int ret;
  201. ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
  202. if (ret)
  203. hang();
  204. ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
  205. if (ret)
  206. hang();
  207. #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
  208. ret = socfpga_get_base_addr("intel,agilex-clkmgr",
  209. &socfpga_clkmgr_base);
  210. #else
  211. ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
  212. #endif
  213. if (ret)
  214. hang();
  215. }
  216. phys_addr_t socfpga_get_rstmgr_addr(void)
  217. {
  218. return socfpga_rstmgr_base;
  219. }
  220. phys_addr_t socfpga_get_sysmgr_addr(void)
  221. {
  222. return socfpga_sysmgr_base;
  223. }
  224. phys_addr_t socfpga_get_clkmgr_addr(void)
  225. {
  226. return socfpga_clkmgr_base;
  227. }