mailbox_s10.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <wait_bit.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/mailbox_s10.h>
  11. #include <asm/arch/system_manager.h>
  12. #include <asm/secure.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #define MBOX_READL(reg) \
  15. readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
  16. #define MBOX_WRITEL(data, reg) \
  17. writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg))
  18. #define MBOX_READ_RESP_BUF(rout) \
  19. MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32)))
  20. #define MBOX_WRITE_CMD_BUF(data, cin) \
  21. MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32)))
  22. static __always_inline int mbox_polling_resp(u32 rout)
  23. {
  24. u32 rin;
  25. unsigned long i = ~0;
  26. while (i) {
  27. rin = MBOX_READL(MBOX_RIN);
  28. if (rout != rin)
  29. return 0;
  30. i--;
  31. }
  32. return -ETIMEDOUT;
  33. }
  34. /* Check for available slot and write to circular buffer.
  35. * It also update command valid offset (cin) register.
  36. */
  37. static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
  38. u32 *arg)
  39. {
  40. u32 cin;
  41. u32 cout;
  42. u32 i;
  43. cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
  44. cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
  45. /* if command buffer is full or not enough free space
  46. * to fit the data. Note, len is in u32 unit.
  47. */
  48. if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
  49. ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
  50. MBOX_CMD_BUFFER_SIZE) < (len + 1))
  51. return -ENOMEM;
  52. /* write header to circular buffer */
  53. MBOX_WRITE_CMD_BUF(header, cin++);
  54. /* wrapping around when it reach the buffer size */
  55. cin %= MBOX_CMD_BUFFER_SIZE;
  56. /* write arguments */
  57. for (i = 0; i < len; i++) {
  58. MBOX_WRITE_CMD_BUF(arg[i], cin++);
  59. /* wrapping around when it reach the buffer size */
  60. cin %= MBOX_CMD_BUFFER_SIZE;
  61. }
  62. /* write command valid offset */
  63. MBOX_WRITEL(cin, MBOX_CIN);
  64. return 0;
  65. }
  66. /* Check the command and fill it into circular buffer */
  67. static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
  68. u8 is_indirect, u32 len,
  69. u32 *arg)
  70. {
  71. u32 header;
  72. int ret;
  73. /* Total length is command + argument length */
  74. if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
  75. return -EINVAL;
  76. if (cmd > MBOX_MAX_CMD_INDEX)
  77. return -EINVAL;
  78. header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
  79. (is_indirect) ? 1 : 0, cmd);
  80. ret = mbox_fill_cmd_circular_buff(header, len, arg);
  81. return ret;
  82. }
  83. /* Send command only without waiting for responses from SDM */
  84. static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
  85. u8 is_indirect, u32 len,
  86. u32 *arg)
  87. {
  88. int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
  89. /* write doorbell */
  90. MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
  91. return ret;
  92. }
  93. /* Return number of responses received in buffer */
  94. static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
  95. {
  96. u32 rin;
  97. u32 rout;
  98. u32 resp_len = 0;
  99. /* clear doorbell from SDM if it was SET */
  100. if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1)
  101. MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
  102. /* read current response offset */
  103. rout = MBOX_READL(MBOX_ROUT);
  104. /* read response valid offset */
  105. rin = MBOX_READL(MBOX_RIN);
  106. while (rin != rout && (resp_len < resp_buf_max_len)) {
  107. /* Response received */
  108. if (resp_buf)
  109. resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout);
  110. rout++;
  111. /* wrapping around when it reach the buffer size */
  112. rout %= MBOX_RESP_BUFFER_SIZE;
  113. /* update next ROUT */
  114. MBOX_WRITEL(rout, MBOX_ROUT);
  115. }
  116. return resp_len;
  117. }
  118. /* Support one command and up to 31 words argument length only */
  119. static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
  120. u32 len, u32 *arg, u8 urgent,
  121. u32 *resp_buf_len,
  122. u32 *resp_buf)
  123. {
  124. u32 rin;
  125. u32 resp;
  126. u32 rout;
  127. u32 status;
  128. u32 resp_len;
  129. u32 buf_len;
  130. int ret;
  131. if (urgent) {
  132. /* Read status because it is toggled */
  133. status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
  134. /* Write urgent command to urgent register */
  135. MBOX_WRITEL(cmd, MBOX_URG);
  136. } else {
  137. ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
  138. if (ret)
  139. return ret;
  140. }
  141. /* write doorbell */
  142. MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
  143. while (1) {
  144. ret = ~0;
  145. /* Wait for doorbell from SDM */
  146. while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--)
  147. ;
  148. if (!ret)
  149. return -ETIMEDOUT;
  150. /* clear interrupt */
  151. MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
  152. if (urgent) {
  153. u32 new_status = MBOX_READL(MBOX_STATUS);
  154. /* Urgent ACK is toggled */
  155. if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
  156. return 0;
  157. return -ECOMM;
  158. }
  159. /* read current response offset */
  160. rout = MBOX_READL(MBOX_ROUT);
  161. /* read response valid offset */
  162. rin = MBOX_READL(MBOX_RIN);
  163. if (rout != rin) {
  164. /* Response received */
  165. resp = MBOX_READ_RESP_BUF(rout);
  166. rout++;
  167. /* wrapping around when it reach the buffer size */
  168. rout %= MBOX_RESP_BUFFER_SIZE;
  169. /* update next ROUT */
  170. MBOX_WRITEL(rout, MBOX_ROUT);
  171. /* check client ID and ID */
  172. if ((MBOX_RESP_CLIENT_GET(resp) ==
  173. MBOX_CLIENT_ID_UBOOT) &&
  174. (MBOX_RESP_ID_GET(resp) == id)) {
  175. ret = MBOX_RESP_ERR_GET(resp);
  176. if (ret)
  177. return ret;
  178. if (resp_buf_len) {
  179. buf_len = *resp_buf_len;
  180. *resp_buf_len = 0;
  181. } else {
  182. buf_len = 0;
  183. }
  184. resp_len = MBOX_RESP_LEN_GET(resp);
  185. while (resp_len) {
  186. ret = mbox_polling_resp(rout);
  187. if (ret)
  188. return ret;
  189. /* we need to process response buffer
  190. * even caller doesn't need it
  191. */
  192. resp = MBOX_READ_RESP_BUF(rout);
  193. rout++;
  194. resp_len--;
  195. rout %= MBOX_RESP_BUFFER_SIZE;
  196. MBOX_WRITEL(rout, MBOX_ROUT);
  197. if (buf_len) {
  198. /* copy response to buffer */
  199. resp_buf[*resp_buf_len] = resp;
  200. (*resp_buf_len)++;
  201. buf_len--;
  202. }
  203. }
  204. return ret;
  205. }
  206. }
  207. };
  208. return -EIO;
  209. }
  210. int mbox_init(void)
  211. {
  212. int ret;
  213. /* enable mailbox interrupts */
  214. MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
  215. /* Ensure urgent request is cleared */
  216. MBOX_WRITEL(0, MBOX_URG);
  217. /* Ensure the Doorbell Interrupt is cleared */
  218. MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
  219. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
  220. NULL, 1, 0, NULL);
  221. if (ret)
  222. return ret;
  223. /* Renable mailbox interrupts after MBOX_RESTART */
  224. MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
  225. return 0;
  226. }
  227. #ifdef CONFIG_CADENCE_QSPI
  228. int mbox_qspi_close(void)
  229. {
  230. return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
  231. 0, NULL, 0, 0, NULL);
  232. }
  233. int mbox_qspi_open(void)
  234. {
  235. int ret;
  236. u32 resp_buf[1];
  237. u32 resp_buf_len;
  238. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
  239. 0, NULL, 0, 0, NULL);
  240. if (ret) {
  241. /* retry again by closing and reopen the QSPI again */
  242. ret = mbox_qspi_close();
  243. if (ret)
  244. return ret;
  245. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
  246. MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
  247. if (ret)
  248. return ret;
  249. }
  250. /* HPS will directly control the QSPI controller, no longer mailbox */
  251. resp_buf_len = 1;
  252. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
  253. 0, NULL, 0, (u32 *)&resp_buf_len,
  254. (u32 *)&resp_buf);
  255. if (ret)
  256. goto error;
  257. /* We are getting QSPI ref clock and set into sysmgr boot register */
  258. printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
  259. writel(resp_buf[0],
  260. socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
  261. return 0;
  262. error:
  263. mbox_qspi_close();
  264. return ret;
  265. }
  266. #endif /* CONFIG_CADENCE_QSPI */
  267. int mbox_reset_cold(void)
  268. {
  269. int ret;
  270. ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
  271. 0, NULL, 0, 0, NULL);
  272. if (ret) {
  273. /* mailbox sent failure, wait for watchdog to kick in */
  274. hang();
  275. }
  276. return 0;
  277. }
  278. /* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
  279. static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
  280. {
  281. u32 reconfig_status_resp_len;
  282. u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
  283. int ret;
  284. reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
  285. ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
  286. MBOX_CMD_DIRECT, 0, NULL, 0,
  287. &reconfig_status_resp_len,
  288. reconfig_status_resp);
  289. if (ret)
  290. return ret;
  291. /* Check for any error */
  292. ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
  293. if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
  294. return ret;
  295. /* Make sure nStatus is not 0 */
  296. ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
  297. if (!(ret & RCF_PIN_STATUS_NSTATUS))
  298. return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
  299. ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
  300. if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
  301. return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
  302. if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
  303. (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
  304. !reconfig_status_resp[RECONFIG_STATUS_STATE])
  305. return 0; /* configuration success */
  306. return MBOX_CFGSTAT_STATE_CONFIG;
  307. }
  308. int mbox_get_fpga_config_status(u32 cmd)
  309. {
  310. return mbox_get_fpga_config_status_common(cmd);
  311. }
  312. int __secure mbox_get_fpga_config_status_psci(u32 cmd)
  313. {
  314. return mbox_get_fpga_config_status_common(cmd);
  315. }
  316. int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
  317. u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
  318. {
  319. return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
  320. resp_buf_len, resp_buf);
  321. }
  322. int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
  323. u32 *arg, u8 urgent, u32 *resp_buf_len,
  324. u32 *resp_buf)
  325. {
  326. return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
  327. resp_buf_len, resp_buf);
  328. }
  329. int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
  330. {
  331. return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
  332. }
  333. int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
  334. u32 *arg)
  335. {
  336. return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
  337. }
  338. int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
  339. {
  340. return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
  341. }
  342. int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
  343. {
  344. return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
  345. }