rk3188.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <hang.h>
  8. #include <syscon.h>
  9. #include <asm/io.h>
  10. #include <asm/arch-rockchip/bootrom.h>
  11. #include <asm/arch-rockchip/clock.h>
  12. #include <asm/arch-rockchip/grf_rk3188.h>
  13. #include <asm/arch-rockchip/hardware.h>
  14. #define GRF_BASE 0x20008000
  15. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  16. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
  17. [BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
  18. };
  19. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  20. void board_debug_uart_init(void)
  21. {
  22. /* Enable early UART on the RK3188 */
  23. struct rk3188_grf * const grf = (void *)GRF_BASE;
  24. enum {
  25. GPIO1B1_SHIFT = 2,
  26. GPIO1B1_MASK = 3,
  27. GPIO1B1_GPIO = 0,
  28. GPIO1B1_UART2_SOUT,
  29. GPIO1B1_JTAG_TDO,
  30. GPIO1B0_SHIFT = 0,
  31. GPIO1B0_MASK = 3,
  32. GPIO1B0_GPIO = 0,
  33. GPIO1B0_UART2_SIN,
  34. GPIO1B0_JTAG_TDI,
  35. };
  36. rk_clrsetreg(&grf->gpio1b_iomux,
  37. GPIO1B1_MASK << GPIO1B1_SHIFT |
  38. GPIO1B0_MASK << GPIO1B0_SHIFT,
  39. GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
  40. GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
  41. }
  42. #endif
  43. #ifdef CONFIG_SPL_BUILD
  44. int arch_cpu_init(void)
  45. {
  46. struct rk3188_grf *grf;
  47. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  48. if (IS_ERR(grf)) {
  49. pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
  50. return 0;
  51. }
  52. #ifdef CONFIG_ROCKCHIP_USB_UART
  53. rk_clrsetreg(&grf->uoc0_con[0],
  54. SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
  55. 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
  56. 1 << COMMON_ON_N_SHIFT);
  57. rk_clrsetreg(&grf->uoc0_con[2],
  58. SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
  59. rk_clrsetreg(&grf->uoc0_con[3],
  60. OPMODE_MASK | XCVRSELECT_MASK |
  61. TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
  62. OPMODE_NODRIVING << OPMODE_SHIFT |
  63. XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
  64. 1 << TERMSEL_FULLSPEED_SHIFT |
  65. 1 << SUSPENDN_SHIFT);
  66. rk_clrsetreg(&grf->uoc0_con[0],
  67. BYPASSSEL_MASK | BYPASSDMEN_MASK,
  68. 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
  69. #endif
  70. /* enable noc remap to mimic legacy loaders */
  71. rk_clrsetreg(&grf->soc_con0,
  72. NOC_REMAP_MASK << NOC_REMAP_SHIFT,
  73. NOC_REMAP_MASK << NOC_REMAP_SHIFT);
  74. return 0;
  75. }
  76. #endif
  77. #ifdef CONFIG_SPL_BUILD
  78. static int setup_led(void)
  79. {
  80. #ifdef CONFIG_SPL_LED
  81. struct udevice *dev;
  82. char *led_name;
  83. int ret;
  84. led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
  85. if (!led_name)
  86. return 0;
  87. ret = led_get_by_label(led_name, &dev);
  88. if (ret) {
  89. debug("%s: get=%d\n", __func__, ret);
  90. return ret;
  91. }
  92. ret = led_set_on(dev, 1);
  93. if (ret)
  94. return ret;
  95. #endif
  96. return 0;
  97. }
  98. void spl_board_init(void)
  99. {
  100. int ret;
  101. ret = setup_led();
  102. if (ret) {
  103. debug("LED ret=%d\n", ret);
  104. hang();
  105. }
  106. }
  107. #endif