dra7xx_iodelay.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015
  4. * Texas Instruments Incorporated, <www.ti.com>
  5. *
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <hang.h>
  10. #include <asm/utils.h>
  11. #include <asm/arch/dra7xx_iodelay.h>
  12. #include <asm/arch/omap.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/mux_dra7xx.h>
  16. #include <asm/omap_common.h>
  17. static int isolate_io(u32 isolate)
  18. {
  19. if (isolate) {
  20. clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
  21. SDCARD_PWRDNZ);
  22. clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
  23. SDCARD_BIAS_PWRDNZ);
  24. }
  25. /* Override control on ISOCLKIN signal to IO pad ring. */
  26. clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
  27. PMCTRL_ISOCLK_OVERRIDE_CTRL);
  28. if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
  29. (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
  30. return ERR_DEISOLATE_IO << isolate;
  31. /* Isolate/Deisolate IO */
  32. clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
  33. isolate << CTRL_ISOLATE_SHIFT);
  34. /* Dummy read to add delay t > 10ns */
  35. readl((*ctrl)->ctrl_core_sma_sw_0);
  36. /* Return control on ISOCLKIN to hardware */
  37. clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
  38. PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
  39. if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
  40. 0 << PMCTRL_ISOCLK_STATUS_SHIFT,
  41. (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
  42. return ERR_DEISOLATE_IO << isolate;
  43. return 0;
  44. }
  45. static int calibrate_iodelay(u32 base)
  46. {
  47. u32 reg;
  48. /* Configure REFCLK period */
  49. reg = readl(base + CFG_REG_2_OFFSET);
  50. reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
  51. reg |= CFG_REG_REFCLK_PERIOD;
  52. writel(reg, base + CFG_REG_2_OFFSET);
  53. /* Initiate Calibration */
  54. clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
  55. CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
  56. if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
  57. (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
  58. return ERR_CALIBRATE_IODELAY;
  59. return 0;
  60. }
  61. static int update_delay_mechanism(u32 base)
  62. {
  63. /* Initiate the reload of calibrated values. */
  64. clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
  65. CFG_REG_ROM_READ_START);
  66. if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
  67. (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
  68. return ERR_UPDATE_DELAY;
  69. return 0;
  70. }
  71. static u32 calculate_delay(u32 base, u16 offset, u16 den)
  72. {
  73. u16 refclk_period, dly_cnt, ref_cnt;
  74. u32 reg, q, r;
  75. refclk_period = readl(base + CFG_REG_2_OFFSET) &
  76. CFG_REG_REFCLK_PERIOD_MASK;
  77. reg = readl(base + offset);
  78. dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
  79. ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
  80. if (!dly_cnt || !den)
  81. return 0;
  82. /*
  83. * To avoid overflow and integer truncation, delay value
  84. * is calculated as quotient + remainder.
  85. */
  86. q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
  87. r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
  88. (2 * dly_cnt * den);
  89. return q + r;
  90. }
  91. static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
  92. {
  93. u32 g_delay_coarse, g_delay_fine;
  94. u32 a_delay_coarse, a_delay_fine;
  95. u32 c_elements, f_elements;
  96. u32 total_delay, reg = 0;
  97. g_delay_coarse = g_delay / 920;
  98. g_delay_fine = ((g_delay % 920) * 10) / 60;
  99. a_delay_coarse = a_delay / cpde;
  100. a_delay_fine = ((a_delay % cpde) * 10) / fpde;
  101. c_elements = g_delay_coarse + a_delay_coarse;
  102. f_elements = (g_delay_fine + a_delay_fine) / 10;
  103. if (f_elements > 22) {
  104. total_delay = c_elements * cpde + f_elements * fpde;
  105. c_elements = total_delay / cpde;
  106. f_elements = (total_delay % cpde) / fpde;
  107. }
  108. reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
  109. reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
  110. reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
  111. reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
  112. return reg;
  113. }
  114. int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
  115. int niodelays)
  116. {
  117. struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
  118. u32 reg, cpde, fpde, i;
  119. if (!niodelays)
  120. return 0;
  121. cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
  122. 88);
  123. if (!cpde)
  124. return ERR_CPDE;
  125. fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
  126. 264);
  127. if (!fpde)
  128. return ERR_FPDE;
  129. for (i = 0; i < niodelays; i++, iodelay++) {
  130. reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
  131. fpde);
  132. writel(reg, base + iodelay->offset);
  133. }
  134. return 0;
  135. }
  136. int __recalibrate_iodelay_start(void)
  137. {
  138. int ret = 0;
  139. /* IO recalibration should be done only from SRAM */
  140. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
  141. puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
  142. return -1;
  143. }
  144. /* unlock IODELAY CONFIG registers */
  145. writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
  146. CFG_REG_8_OFFSET);
  147. ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
  148. if (ret)
  149. goto err;
  150. ret = isolate_io(ISOLATE_IO);
  151. if (ret)
  152. goto err;
  153. ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
  154. err:
  155. return ret;
  156. }
  157. void __recalibrate_iodelay_end(int ret)
  158. {
  159. /* IO recalibration should be done only from SRAM */
  160. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
  161. puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
  162. return;
  163. }
  164. /* Deisolate IO if it is already isolated */
  165. if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK)
  166. isolate_io(DEISOLATE_IO);
  167. /* lock IODELAY CONFIG registers */
  168. writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
  169. CFG_REG_8_OFFSET);
  170. /*
  171. * UART cannot be used during IO recalibration sequence as IOs are in
  172. * isolation. So error handling and debug prints are done after
  173. * complete IO delay recalibration sequence
  174. */
  175. switch (ret) {
  176. case ERR_CALIBRATE_IODELAY:
  177. puts("IODELAY: IO delay calibration sequence failed\n");
  178. break;
  179. case ERR_ISOLATE_IO:
  180. puts("IODELAY: Isolation of Device IOs failed\n");
  181. break;
  182. case ERR_UPDATE_DELAY:
  183. puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
  184. break;
  185. case ERR_DEISOLATE_IO:
  186. puts("IODELAY: De-isolation of Device IOs failed\n");
  187. break;
  188. case ERR_CPDE:
  189. puts("IODELAY: CPDE calculation failed\n");
  190. break;
  191. case ERR_FPDE:
  192. puts("IODELAY: FPDE calculation failed\n");
  193. break;
  194. case -1:
  195. puts("IODELAY: Wrong Context call?\n");
  196. break;
  197. default:
  198. debug("IODELAY: IO delay recalibration successfully completed\n");
  199. }
  200. /* If there is an error during iodelay recalibration, SoC is in a bad
  201. * state. Do not progress any further.
  202. */
  203. if (ret)
  204. hang();
  205. return;
  206. }
  207. void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
  208. struct iodelay_cfg_entry const *iodelay,
  209. int niodelays)
  210. {
  211. int ret = 0;
  212. /* IO recalibration should be done only from SRAM */
  213. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
  214. puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
  215. return;
  216. }
  217. ret = __recalibrate_iodelay_start();
  218. if (ret)
  219. goto err;
  220. /* Configure Mux settings */
  221. do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
  222. /* Configure Manual IO timing modes */
  223. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  224. if (ret)
  225. goto err;
  226. err:
  227. __recalibrate_iodelay_end(ret);
  228. }
  229. void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
  230. struct iodelay_cfg_entry const *iodelay,
  231. int niodelays)
  232. {
  233. int ret = 0;
  234. /* unlock IODELAY CONFIG registers */
  235. writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
  236. CFG_REG_8_OFFSET);
  237. ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
  238. if (ret)
  239. goto err;
  240. ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
  241. /* Configure Mux settings */
  242. do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
  243. /* Configure Manual IO timing modes */
  244. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  245. if (ret)
  246. goto err;
  247. err:
  248. /* lock IODELAY CONFIG registers */
  249. writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
  250. CFG_REG_8_OFFSET);
  251. }