ddr.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Gateworks Corporation
  4. * Author: Tim Harvey <tharvey@gateworks.com>
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <linux/types.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/mx6-ddr.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. #include <asm/types.h>
  14. #include <wait_bit.h>
  15. #if defined(CONFIG_MX6_DDRCAL)
  16. static void reset_read_data_fifos(void)
  17. {
  18. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  19. /* Reset data FIFOs twice. */
  20. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  21. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  22. setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
  23. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
  24. }
  25. static void precharge_all(const bool cs0_enable, const bool cs1_enable)
  26. {
  27. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  28. /*
  29. * Issue the Precharge-All command to the DDR device for both
  30. * chip selects. Note, CON_REQ bit should also remain set. If
  31. * only using one chip select, then precharge only the desired
  32. * chip select.
  33. */
  34. if (cs0_enable) { /* CS0 */
  35. writel(0x04008050, &mmdc0->mdscr);
  36. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  37. }
  38. if (cs1_enable) { /* CS1 */
  39. writel(0x04008058, &mmdc0->mdscr);
  40. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  41. }
  42. }
  43. static void force_delay_measurement(int bus_size)
  44. {
  45. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  46. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  47. writel(0x800, &mmdc0->mpmur0);
  48. if (bus_size == 0x2)
  49. writel(0x800, &mmdc1->mpmur0);
  50. }
  51. static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
  52. {
  53. u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
  54. /*
  55. * DQS gating absolute offset should be modified from reflecting
  56. * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
  57. */
  58. val_ctrl = readl(reg_ctrl);
  59. val_ctrl &= 0xf0000000;
  60. dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
  61. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  62. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  63. val_ctrl |= dg_dl_abs_offset + dg_hc_del;
  64. dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
  65. dg_dl_abs_offset = dg_tmp_val & 0x7f;
  66. dg_hc_del = (dg_tmp_val & 0x780) << 1;
  67. val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
  68. writel(val_ctrl, reg_ctrl);
  69. }
  70. static void correct_mpwldectr_result(void *reg)
  71. {
  72. /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
  73. const unsigned int limit = 0x148;
  74. u32 val = readl(reg);
  75. u32 old = val;
  76. if ((val & 0x17f) > limit)
  77. val &= 0xffff << 16;
  78. if (((val >> 16) & 0x17f) > limit)
  79. val &= 0xffff;
  80. if (old != val)
  81. writel(val, reg);
  82. }
  83. int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  84. {
  85. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  86. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  87. u32 esdmisc_val, zq_val;
  88. u32 errors = 0;
  89. u32 ldectrl[4] = {0};
  90. u32 ddr_mr1 = 0x4;
  91. u32 rwalat_max;
  92. /*
  93. * Stash old values in case calibration fails,
  94. * we need to restore them
  95. */
  96. ldectrl[0] = readl(&mmdc0->mpwldectrl0);
  97. ldectrl[1] = readl(&mmdc0->mpwldectrl1);
  98. if (sysinfo->dsize == 2) {
  99. ldectrl[2] = readl(&mmdc1->mpwldectrl0);
  100. ldectrl[3] = readl(&mmdc1->mpwldectrl1);
  101. }
  102. /* disable DDR logic power down timer */
  103. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  104. /* disable Adopt power down timer */
  105. setbits_le32(&mmdc0->mapsr, 0x1);
  106. debug("Starting write leveling calibration.\n");
  107. /*
  108. * 2. disable auto refresh and ZQ calibration
  109. * before proceeding with Write Leveling calibration
  110. */
  111. esdmisc_val = readl(&mmdc0->mdref);
  112. writel(0x0000C000, &mmdc0->mdref);
  113. zq_val = readl(&mmdc0->mpzqhwctrl);
  114. writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
  115. /* 3. increase walat and ralat to maximum */
  116. rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
  117. setbits_le32(&mmdc0->mdmisc, rwalat_max);
  118. if (sysinfo->dsize == 2)
  119. setbits_le32(&mmdc1->mdmisc, rwalat_max);
  120. /*
  121. * 4 & 5. Configure the external DDR device to enter write-leveling
  122. * mode through Load Mode Register command.
  123. * Register setting:
  124. * Bits[31:16] MR1 value (0x0080 write leveling enable)
  125. * Bit[9] set WL_EN to enable MMDC DQS output
  126. * Bits[6:4] set CMD bits for Load Mode Register programming
  127. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  128. */
  129. writel(0x00808231, &mmdc0->mdscr);
  130. /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
  131. writel(0x00000001, &mmdc0->mpwlgcr);
  132. /*
  133. * 7. Upon completion of this process the MMDC de-asserts
  134. * the MPWLGCR[HW_WL_EN]
  135. */
  136. wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
  137. /*
  138. * 8. check for any errors: check both PHYs for x64 configuration,
  139. * if x32, check only PHY0
  140. */
  141. if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
  142. errors |= 1;
  143. if (sysinfo->dsize == 2)
  144. if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
  145. errors |= 2;
  146. debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
  147. /* check to see if cal failed */
  148. if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
  149. (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
  150. ((sysinfo->dsize < 2) ||
  151. ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
  152. (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
  153. debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
  154. writel(ldectrl[0], &mmdc0->mpwldectrl0);
  155. writel(ldectrl[1], &mmdc0->mpwldectrl1);
  156. if (sysinfo->dsize == 2) {
  157. writel(ldectrl[2], &mmdc1->mpwldectrl0);
  158. writel(ldectrl[3], &mmdc1->mpwldectrl1);
  159. }
  160. errors |= 4;
  161. }
  162. correct_mpwldectr_result(&mmdc0->mpwldectrl0);
  163. correct_mpwldectr_result(&mmdc0->mpwldectrl1);
  164. if (sysinfo->dsize == 2) {
  165. correct_mpwldectr_result(&mmdc1->mpwldectrl0);
  166. correct_mpwldectr_result(&mmdc1->mpwldectrl1);
  167. }
  168. /*
  169. * User should issue MRS command to exit write leveling mode
  170. * through Load Mode Register command
  171. * Register setting:
  172. * Bits[31:16] MR1 value "ddr_mr1" value from initialization
  173. * Bit[9] clear WL_EN to disable MMDC DQS output
  174. * Bits[6:4] set CMD bits for Load Mode Register programming
  175. * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
  176. */
  177. writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
  178. /* re-enable auto refresh and zq cal */
  179. writel(esdmisc_val, &mmdc0->mdref);
  180. writel(zq_val, &mmdc0->mpzqhwctrl);
  181. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  182. readl(&mmdc0->mpwldectrl0));
  183. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  184. readl(&mmdc0->mpwldectrl1));
  185. if (sysinfo->dsize == 2) {
  186. debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
  187. readl(&mmdc1->mpwldectrl0));
  188. debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
  189. readl(&mmdc1->mpwldectrl1));
  190. }
  191. /* We must force a readback of these values, to get them to stick */
  192. readl(&mmdc0->mpwldectrl0);
  193. readl(&mmdc0->mpwldectrl1);
  194. if (sysinfo->dsize == 2) {
  195. readl(&mmdc1->mpwldectrl0);
  196. readl(&mmdc1->mpwldectrl1);
  197. }
  198. /* enable DDR logic power down timer: */
  199. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  200. /* Enable Adopt power down timer: */
  201. clrbits_le32(&mmdc0->mapsr, 0x1);
  202. /* Clear CON_REQ */
  203. writel(0, &mmdc0->mdscr);
  204. return errors;
  205. }
  206. static void mmdc_set_sdqs(bool set)
  207. {
  208. struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
  209. (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  210. struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
  211. (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  212. int i, sdqs_cnt;
  213. u32 sdqs;
  214. if (is_mx6sx()) {
  215. sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
  216. sdqs_cnt = 2;
  217. } else { /* MX6DQ */
  218. sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
  219. sdqs_cnt = 8;
  220. }
  221. for (i = 0; i < sdqs_cnt; i++) {
  222. if (set)
  223. setbits_le32(sdqs + (4 * i), 0x7000);
  224. else
  225. clrbits_le32(sdqs + (4 * i), 0x7000);
  226. }
  227. }
  228. int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
  229. {
  230. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  231. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  232. bool cs0_enable;
  233. bool cs1_enable;
  234. bool cs0_enable_initial;
  235. bool cs1_enable_initial;
  236. u32 esdmisc_val;
  237. u32 temp_ref;
  238. u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
  239. u32 errors = 0;
  240. u32 initdelay = 0x40404040;
  241. /* check to see which chip selects are enabled */
  242. cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
  243. cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
  244. /* disable DDR logic power down timer: */
  245. clrbits_le32(&mmdc0->mdpdc, 0xff00);
  246. /* disable Adopt power down timer: */
  247. setbits_le32(&mmdc0->mapsr, 0x1);
  248. /* set DQS pull ups */
  249. mmdc_set_sdqs(true);
  250. /* Save old RALAT and WALAT values */
  251. esdmisc_val = readl(&mmdc0->mdmisc);
  252. setbits_le32(&mmdc0->mdmisc,
  253. (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
  254. /* Disable auto refresh before proceeding with calibration */
  255. temp_ref = readl(&mmdc0->mdref);
  256. writel(0x0000c000, &mmdc0->mdref);
  257. /*
  258. * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
  259. * this also sets the CON_REQ bit.
  260. */
  261. if (cs0_enable_initial)
  262. writel(0x00008020, &mmdc0->mdscr);
  263. if (cs1_enable_initial)
  264. writel(0x00008028, &mmdc0->mdscr);
  265. /* poll to make sure the con_ack bit was asserted */
  266. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
  267. /*
  268. * Check MDMISC register CALIB_PER_CS to see which CS calibration
  269. * is targeted to (under normal cases, it should be cleared
  270. * as this is the default value, indicating calibration is directed
  271. * to CS0).
  272. * Disable the other chip select not being target for calibration
  273. * to avoid any potential issues. This will get re-enabled at end
  274. * of calibration.
  275. */
  276. if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
  277. clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
  278. else
  279. clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
  280. /*
  281. * Check to see which chip selects are now enabled for
  282. * the remainder of the calibration.
  283. */
  284. cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
  285. cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
  286. precharge_all(cs0_enable, cs1_enable);
  287. /* Write the pre-defined value into MPPDCMPR1 */
  288. writel(pddword, &mmdc0->mppdcmpr1);
  289. /*
  290. * Issue a write access to the external DDR device by setting
  291. * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
  292. * this bit until it clears to indicate completion of the write access.
  293. */
  294. setbits_le32(&mmdc0->mpswdar0, 1);
  295. wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
  296. /* Set the RD_DL_ABS# bits to their default values
  297. * (will be calibrated later in the read delay-line calibration).
  298. * Both PHYs for x64 configuration, if x32, do only PHY0.
  299. */
  300. writel(initdelay, &mmdc0->mprddlctl);
  301. if (sysinfo->dsize == 0x2)
  302. writel(initdelay, &mmdc1->mprddlctl);
  303. /* Force a measurment, for previous delay setup to take effect. */
  304. force_delay_measurement(sysinfo->dsize);
  305. /*
  306. * ***************************
  307. * Read DQS Gating calibration
  308. * ***************************
  309. */
  310. debug("Starting Read DQS Gating calibration.\n");
  311. /*
  312. * Reset the read data FIFOs (two resets); only need to issue reset
  313. * to PHY0 since in x64 mode, the reset will also go to PHY1.
  314. */
  315. reset_read_data_fifos();
  316. /*
  317. * Start the automatic read DQS gating calibration process by
  318. * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
  319. * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
  320. * to indicate completion.
  321. * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
  322. * no errors were seen during calibration.
  323. */
  324. /*
  325. * Set bit 30: chooses option to wait 32 cycles instead of
  326. * 16 before comparing read data.
  327. */
  328. setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  329. if (sysinfo->dsize == 2)
  330. setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  331. /* Set bit 28 to start automatic read DQS gating calibration */
  332. setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
  333. /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
  334. wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
  335. /*
  336. * Check to see if any errors were encountered during calibration
  337. * (check MPDGCTRL0[HW_DG_ERR]).
  338. * Check both PHYs for x64 configuration, if x32, check only PHY0.
  339. */
  340. if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
  341. errors |= 1;
  342. if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
  343. errors |= 2;
  344. /* now disable mpdgctrl0[DG_CMP_CYC] */
  345. clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
  346. if (sysinfo->dsize == 2)
  347. clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
  348. /*
  349. * DQS gating absolute offset should be modified from
  350. * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
  351. * reflecting (HW_DG_UPx - 0x80)
  352. */
  353. modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
  354. &mmdc0->mpdgctrl0);
  355. modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
  356. &mmdc0->mpdgctrl1);
  357. if (sysinfo->dsize == 0x2) {
  358. modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
  359. &mmdc1->mpdgctrl0);
  360. modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
  361. &mmdc1->mpdgctrl1);
  362. }
  363. debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
  364. /*
  365. * **********************
  366. * Read Delay calibration
  367. * **********************
  368. */
  369. debug("Starting Read Delay calibration.\n");
  370. reset_read_data_fifos();
  371. /*
  372. * 4. Issue the Precharge-All command to the DDR device for both
  373. * chip selects. If only using one chip select, then precharge
  374. * only the desired chip select.
  375. */
  376. precharge_all(cs0_enable, cs1_enable);
  377. /*
  378. * 9. Read delay-line calibration
  379. * Start the automatic read calibration process by asserting
  380. * MPRDDLHWCTL[HW_RD_DL_EN].
  381. */
  382. writel(0x00000030, &mmdc0->mprddlhwctl);
  383. /*
  384. * 10. poll for completion
  385. * MMDC indicates that the write data calibration had finished by
  386. * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
  387. * no error bits were set.
  388. */
  389. wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
  390. /* check both PHYs for x64 configuration, if x32, check only PHY0 */
  391. if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
  392. errors |= 4;
  393. if ((sysinfo->dsize == 0x2) &&
  394. (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
  395. errors |= 8;
  396. debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
  397. /*
  398. * ***********************
  399. * Write Delay Calibration
  400. * ***********************
  401. */
  402. debug("Starting Write Delay calibration.\n");
  403. reset_read_data_fifos();
  404. /*
  405. * 4. Issue the Precharge-All command to the DDR device for both
  406. * chip selects. If only using one chip select, then precharge
  407. * only the desired chip select.
  408. */
  409. precharge_all(cs0_enable, cs1_enable);
  410. /*
  411. * 8. Set the WR_DL_ABS# bits to their default values.
  412. * Both PHYs for x64 configuration, if x32, do only PHY0.
  413. */
  414. writel(initdelay, &mmdc0->mpwrdlctl);
  415. if (sysinfo->dsize == 0x2)
  416. writel(initdelay, &mmdc1->mpwrdlctl);
  417. /*
  418. * XXX This isn't in the manual. Force a measurement,
  419. * for previous delay setup to effect.
  420. */
  421. force_delay_measurement(sysinfo->dsize);
  422. /*
  423. * 9. 10. Start the automatic write calibration process
  424. * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
  425. */
  426. writel(0x00000030, &mmdc0->mpwrdlhwctl);
  427. /*
  428. * Poll for completion.
  429. * MMDC indicates that the write data calibration had finished
  430. * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
  431. * Also, ensure that no error bits were set.
  432. */
  433. wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
  434. /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
  435. if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
  436. errors |= 16;
  437. if ((sysinfo->dsize == 0x2) &&
  438. (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
  439. errors |= 32;
  440. debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
  441. reset_read_data_fifos();
  442. /* Enable DDR logic power down timer */
  443. setbits_le32(&mmdc0->mdpdc, 0x00005500);
  444. /* Enable Adopt power down timer */
  445. clrbits_le32(&mmdc0->mapsr, 0x1);
  446. /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
  447. writel(esdmisc_val, &mmdc0->mdmisc);
  448. /* Clear DQS pull ups */
  449. mmdc_set_sdqs(false);
  450. /* Re-enable SDE (chip selects) if they were set initially */
  451. if (cs1_enable_initial)
  452. /* Set SDE_1 */
  453. setbits_le32(&mmdc0->mdctl, 1 << 30);
  454. if (cs0_enable_initial)
  455. /* Set SDE_0 */
  456. setbits_le32(&mmdc0->mdctl, 1 << 31);
  457. /* Re-enable to auto refresh */
  458. writel(temp_ref, &mmdc0->mdref);
  459. /* Clear the MDSCR (including the con_req bit) */
  460. writel(0x0, &mmdc0->mdscr); /* CS0 */
  461. /* Poll to make sure the con_ack bit is clear */
  462. wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
  463. /*
  464. * Print out the registers that were updated as a result
  465. * of the calibration process.
  466. */
  467. debug("MMDC registers updated from calibration\n");
  468. debug("Read DQS gating calibration:\n");
  469. debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
  470. debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
  471. if (sysinfo->dsize == 2) {
  472. debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
  473. debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
  474. }
  475. debug("Read calibration:\n");
  476. debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
  477. if (sysinfo->dsize == 2)
  478. debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
  479. debug("Write calibration:\n");
  480. debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
  481. if (sysinfo->dsize == 2)
  482. debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
  483. /*
  484. * Registers below are for debugging purposes. These print out
  485. * the upper and lower boundaries captured during
  486. * read DQS gating calibration.
  487. */
  488. debug("Status registers bounds for read DQS gating:\n");
  489. debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
  490. debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
  491. debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
  492. debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
  493. if (sysinfo->dsize == 2) {
  494. debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
  495. debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
  496. debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
  497. debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
  498. }
  499. debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
  500. return errors;
  501. }
  502. #endif
  503. #if defined(CONFIG_MX6SX)
  504. /* Configure MX6SX mmdc iomux */
  505. void mx6sx_dram_iocfg(unsigned width,
  506. const struct mx6sx_iomux_ddr_regs *ddr,
  507. const struct mx6sx_iomux_grp_regs *grp)
  508. {
  509. struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
  510. struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
  511. mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
  512. mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
  513. /* DDR IO TYPE */
  514. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  515. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  516. /* CLOCK */
  517. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  518. /* ADDRESS */
  519. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  520. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  521. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  522. /* Control */
  523. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  524. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  525. writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
  526. writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
  527. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  528. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  529. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  530. /* Data Strobes */
  531. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  532. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  533. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  534. if (width >= 32) {
  535. writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
  536. writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
  537. }
  538. /* Data */
  539. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  540. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  541. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  542. if (width >= 32) {
  543. writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
  544. writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
  545. }
  546. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  547. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  548. if (width >= 32) {
  549. writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
  550. writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
  551. }
  552. }
  553. #endif
  554. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  555. void mx6ul_dram_iocfg(unsigned width,
  556. const struct mx6ul_iomux_ddr_regs *ddr,
  557. const struct mx6ul_iomux_grp_regs *grp)
  558. {
  559. struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
  560. struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
  561. mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
  562. mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
  563. /* DDR IO TYPE */
  564. writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
  565. writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
  566. /* CLOCK */
  567. writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
  568. /* ADDRESS */
  569. writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
  570. writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
  571. writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
  572. /* Control */
  573. writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
  574. writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
  575. writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
  576. writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
  577. writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
  578. /* Data Strobes */
  579. writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
  580. writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
  581. writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
  582. /* Data */
  583. writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
  584. writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
  585. writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
  586. writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
  587. writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
  588. }
  589. #endif
  590. #if defined(CONFIG_MX6SL)
  591. void mx6sl_dram_iocfg(unsigned width,
  592. const struct mx6sl_iomux_ddr_regs *ddr,
  593. const struct mx6sl_iomux_grp_regs *grp)
  594. {
  595. struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
  596. struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
  597. mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
  598. mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
  599. /* DDR IO TYPE */
  600. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  601. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  602. /* CLOCK */
  603. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  604. /* ADDRESS */
  605. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  606. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  607. mx6_grp_iomux->grp_addds = grp->grp_addds;
  608. /* Control */
  609. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  610. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  611. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  612. /* Data Strobes */
  613. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  614. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  615. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  616. if (width >= 32) {
  617. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  618. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  619. }
  620. /* Data */
  621. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  622. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  623. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  624. if (width >= 32) {
  625. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  626. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  627. }
  628. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  629. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  630. if (width >= 32) {
  631. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  632. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  633. }
  634. }
  635. #endif
  636. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
  637. /* Configure MX6DQ mmdc iomux */
  638. void mx6dq_dram_iocfg(unsigned width,
  639. const struct mx6dq_iomux_ddr_regs *ddr,
  640. const struct mx6dq_iomux_grp_regs *grp)
  641. {
  642. volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
  643. volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
  644. mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
  645. mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
  646. /* DDR IO Type */
  647. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  648. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  649. /* Clock */
  650. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  651. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  652. /* Address */
  653. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  654. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  655. mx6_grp_iomux->grp_addds = grp->grp_addds;
  656. /* Control */
  657. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  658. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  659. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  660. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  661. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  662. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  663. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  664. /* Data Strobes */
  665. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  666. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  667. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  668. if (width >= 32) {
  669. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  670. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  671. }
  672. if (width >= 64) {
  673. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  674. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  675. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  676. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  677. }
  678. /* Data */
  679. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  680. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  681. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  682. if (width >= 32) {
  683. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  684. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  685. }
  686. if (width >= 64) {
  687. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  688. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  689. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  690. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  691. }
  692. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  693. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  694. if (width >= 32) {
  695. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  696. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  697. }
  698. if (width >= 64) {
  699. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  700. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  701. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  702. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  703. }
  704. }
  705. #endif
  706. #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
  707. /* Configure MX6SDL mmdc iomux */
  708. void mx6sdl_dram_iocfg(unsigned width,
  709. const struct mx6sdl_iomux_ddr_regs *ddr,
  710. const struct mx6sdl_iomux_grp_regs *grp)
  711. {
  712. volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
  713. volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
  714. mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
  715. mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
  716. /* DDR IO Type */
  717. mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
  718. mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
  719. /* Clock */
  720. mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
  721. mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
  722. /* Address */
  723. mx6_ddr_iomux->dram_cas = ddr->dram_cas;
  724. mx6_ddr_iomux->dram_ras = ddr->dram_ras;
  725. mx6_grp_iomux->grp_addds = grp->grp_addds;
  726. /* Control */
  727. mx6_ddr_iomux->dram_reset = ddr->dram_reset;
  728. mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
  729. mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
  730. mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
  731. mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
  732. mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
  733. mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
  734. /* Data Strobes */
  735. mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
  736. mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
  737. mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
  738. if (width >= 32) {
  739. mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
  740. mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
  741. }
  742. if (width >= 64) {
  743. mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
  744. mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
  745. mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
  746. mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
  747. }
  748. /* Data */
  749. mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
  750. mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
  751. mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
  752. if (width >= 32) {
  753. mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
  754. mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
  755. }
  756. if (width >= 64) {
  757. mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
  758. mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
  759. mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
  760. mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
  761. }
  762. mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
  763. mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
  764. if (width >= 32) {
  765. mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
  766. mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
  767. }
  768. if (width >= 64) {
  769. mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
  770. mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
  771. mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
  772. mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
  773. }
  774. }
  775. #endif
  776. /*
  777. * Configure mx6 mmdc registers based on:
  778. * - board-specific memory configuration
  779. * - board-specific calibration data
  780. * - ddr3/lpddr2 chip details
  781. *
  782. * The various calculations here are derived from the Freescale
  783. * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
  784. * MMDC configuration registers based on memory system and memory chip
  785. * parameters.
  786. *
  787. * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
  788. * configuration registers based on memory system and memory chip
  789. * parameters.
  790. *
  791. * The defaults here are those which were specified in the spreadsheet.
  792. * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
  793. * and/or IMX6SLRM section titled MMDC initialization.
  794. */
  795. #define MR(val, ba, cmd, cs1) \
  796. ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
  797. #define MMDC1(entry, value) do { \
  798. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
  799. mmdc1->entry = value; \
  800. } while (0)
  801. /*
  802. * According JESD209-2B-LPDDR2: Table 103
  803. * WL: write latency
  804. */
  805. static int lpddr2_wl(uint32_t mem_speed)
  806. {
  807. switch (mem_speed) {
  808. case 1066:
  809. case 933:
  810. return 4;
  811. case 800:
  812. return 3;
  813. case 677:
  814. case 533:
  815. return 2;
  816. case 400:
  817. case 333:
  818. return 1;
  819. default:
  820. puts("invalid memory speed\n");
  821. hang();
  822. }
  823. return 0;
  824. }
  825. /*
  826. * According JESD209-2B-LPDDR2: Table 103
  827. * RL: read latency
  828. */
  829. static int lpddr2_rl(uint32_t mem_speed)
  830. {
  831. switch (mem_speed) {
  832. case 1066:
  833. return 8;
  834. case 933:
  835. return 7;
  836. case 800:
  837. return 6;
  838. case 677:
  839. return 5;
  840. case 533:
  841. return 4;
  842. case 400:
  843. case 333:
  844. return 3;
  845. default:
  846. puts("invalid memory speed\n");
  847. hang();
  848. }
  849. return 0;
  850. }
  851. void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  852. const struct mx6_mmdc_calibration *calib,
  853. const struct mx6_lpddr2_cfg *lpddr2_cfg)
  854. {
  855. volatile struct mmdc_p_regs *mmdc0;
  856. u32 val;
  857. u8 tcke, tcksrx, tcksre, trrd;
  858. u8 twl, txp, tfaw, tcl;
  859. u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
  860. u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
  861. u16 cs0_end;
  862. u8 coladdr;
  863. int clkper; /* clock period in picoseconds */
  864. int clock; /* clock freq in mHz */
  865. int cs;
  866. /* only support 16/32 bits */
  867. if (sysinfo->dsize > 1)
  868. hang();
  869. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  870. clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
  871. clkper = (1000 * 1000) / clock; /* pico seconds */
  872. twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
  873. /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
  874. switch (lpddr2_cfg->density) {
  875. case 1:
  876. case 2:
  877. case 4:
  878. trfc = DIV_ROUND_UP(130000, clkper) - 1;
  879. txsr = DIV_ROUND_UP(140000, clkper) - 1;
  880. break;
  881. case 8:
  882. trfc = DIV_ROUND_UP(210000, clkper) - 1;
  883. txsr = DIV_ROUND_UP(220000, clkper) - 1;
  884. break;
  885. default:
  886. /*
  887. * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
  888. */
  889. hang();
  890. break;
  891. }
  892. /*
  893. * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
  894. * set them to 0. */
  895. txp = DIV_ROUND_UP(7500, clkper) - 1;
  896. tcke = 3;
  897. if (lpddr2_cfg->mem_speed == 333)
  898. tfaw = DIV_ROUND_UP(60000, clkper) - 1;
  899. else
  900. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  901. trrd = DIV_ROUND_UP(10000, clkper) - 1;
  902. /* tckesr for LPDDR2 */
  903. tcksre = DIV_ROUND_UP(15000, clkper);
  904. tcksrx = tcksre;
  905. twr = DIV_ROUND_UP(15000, clkper) - 1;
  906. /*
  907. * tMRR: 2, tMRW: 5
  908. * tMRD should be set to max(tMRR, tMRW)
  909. */
  910. tmrd = 5;
  911. tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
  912. /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
  913. trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
  914. trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
  915. clkper / 10) - 1;
  916. trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
  917. trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
  918. /* To LPDDR2, CL in MDCFG0 refers to RL */
  919. tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
  920. twtr = DIV_ROUND_UP(7500, clkper) - 1;
  921. trtp = DIV_ROUND_UP(7500, clkper) - 1;
  922. cs0_end = 4 * sysinfo->cs_density - 1;
  923. debug("density:%d Gb (%d Gb per chip)\n",
  924. sysinfo->cs_density, lpddr2_cfg->density);
  925. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  926. debug("memspd:%d\n", lpddr2_cfg->mem_speed);
  927. debug("trcd_lp=%d\n", trcd_lp);
  928. debug("trppb_lp=%d\n", trppb_lp);
  929. debug("trpab_lp=%d\n", trpab_lp);
  930. debug("trc_lp=%d\n", trc_lp);
  931. debug("tcke=%d\n", tcke);
  932. debug("tcksrx=%d\n", tcksrx);
  933. debug("tcksre=%d\n", tcksre);
  934. debug("trfc=%d\n", trfc);
  935. debug("txsr=%d\n", txsr);
  936. debug("txp=%d\n", txp);
  937. debug("tfaw=%d\n", tfaw);
  938. debug("tcl=%d\n", tcl);
  939. debug("tras=%d\n", tras);
  940. debug("twr=%d\n", twr);
  941. debug("tmrd=%d\n", tmrd);
  942. debug("twl=%d\n", twl);
  943. debug("trtp=%d\n", trtp);
  944. debug("twtr=%d\n", twtr);
  945. debug("trrd=%d\n", trrd);
  946. debug("cs0_end=%d\n", cs0_end);
  947. debug("ncs=%d\n", sysinfo->ncs);
  948. /*
  949. * board-specific configuration:
  950. * These values are determined empirically and vary per board layout
  951. */
  952. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  953. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  954. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  955. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  956. mmdc0->mprddlctl = calib->p0_mprddlctl;
  957. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  958. mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
  959. /* Read data DQ Byte0-3 delay */
  960. mmdc0->mprddqby0dl = 0x33333333;
  961. mmdc0->mprddqby1dl = 0x33333333;
  962. if (sysinfo->dsize > 0) {
  963. mmdc0->mprddqby2dl = 0x33333333;
  964. mmdc0->mprddqby3dl = 0x33333333;
  965. }
  966. /* Write data DQ Byte0-3 delay */
  967. mmdc0->mpwrdqby0dl = 0xf3333333;
  968. mmdc0->mpwrdqby1dl = 0xf3333333;
  969. if (sysinfo->dsize > 0) {
  970. mmdc0->mpwrdqby2dl = 0xf3333333;
  971. mmdc0->mpwrdqby3dl = 0xf3333333;
  972. }
  973. /*
  974. * In LPDDR2 mode this register should be cleared,
  975. * so no termination will be activated.
  976. */
  977. mmdc0->mpodtctrl = 0;
  978. /* complete calibration */
  979. val = (1 << 11); /* Force measurement on delay-lines */
  980. mmdc0->mpmur0 = val;
  981. /* Step 1: configuration request */
  982. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  983. /* Step 2: Timing configuration */
  984. mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
  985. (tfaw << 4) | tcl;
  986. mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
  987. mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
  988. mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
  989. (trppb_lp << 4) | trpab_lp;
  990. mmdc0->mdotc = 0;
  991. mmdc0->mdasp = cs0_end; /* CS addressing */
  992. /* Step 3: Configure DDR type */
  993. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  994. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  995. (sysinfo->ralat << 6) | (1 << 3);
  996. /* Step 4: Configure delay while leaving reset */
  997. mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
  998. (sysinfo->rst_to_cke << 0);
  999. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1000. coladdr = lpddr2_cfg->coladdr;
  1001. if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1002. coladdr += 4;
  1003. else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1004. coladdr += 1;
  1005. mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
  1006. (coladdr - 9) << 20 | /* COL */
  1007. (0 << 19) | /* Burst Length = 4 for LPDDR2 */
  1008. (sysinfo->dsize << 16); /* DDR data bus size */
  1009. /* Step 6: Perform ZQ calibration */
  1010. val = 0xa1390003; /* one-time HW ZQ calib */
  1011. mmdc0->mpzqhwctrl = val;
  1012. /* Step 7: Enable MMDC with desired chip select */
  1013. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1014. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1015. /* Step 8: Write Mode Registers to Init LPDDR2 devices */
  1016. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1017. /* MR63: reset */
  1018. mmdc0->mdscr = MR(63, 0, 3, cs);
  1019. /* MR10: calibration,
  1020. * 0xff is calibration command after intilization.
  1021. */
  1022. val = 0xA | (0xff << 8);
  1023. mmdc0->mdscr = MR(val, 0, 3, cs);
  1024. /* MR1 */
  1025. val = 0x1 | (0x82 << 8);
  1026. mmdc0->mdscr = MR(val, 0, 3, cs);
  1027. /* MR2 */
  1028. val = 0x2 | (0x04 << 8);
  1029. mmdc0->mdscr = MR(val, 0, 3, cs);
  1030. /* MR3 */
  1031. val = 0x3 | (0x02 << 8);
  1032. mmdc0->mdscr = MR(val, 0, 3, cs);
  1033. }
  1034. /* Step 10: Power down control and self-refresh */
  1035. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1036. 5 << 12 | /* PWDT_1: 256 cycles */
  1037. 5 << 8 | /* PWDT_0: 256 cycles */
  1038. 1 << 6 | /* BOTH_CS_PD */
  1039. (tcksrx & 0x7) << 3 |
  1040. (tcksre & 0x7);
  1041. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1042. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1043. val = 0xa1310003;
  1044. mmdc0->mpzqhwctrl = val;
  1045. /* Step 12: Configure and activate periodic refresh */
  1046. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1047. /* Step 13: Deassert config request - init complete */
  1048. mmdc0->mdscr = 0x00000000;
  1049. /* wait for auto-ZQ calibration to complete */
  1050. mdelay(1);
  1051. }
  1052. void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1053. const struct mx6_mmdc_calibration *calib,
  1054. const struct mx6_ddr3_cfg *ddr3_cfg)
  1055. {
  1056. volatile struct mmdc_p_regs *mmdc0;
  1057. volatile struct mmdc_p_regs *mmdc1;
  1058. u32 val;
  1059. u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
  1060. u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
  1061. u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
  1062. u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
  1063. u16 cs0_end;
  1064. u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
  1065. u8 coladdr;
  1066. int clkper; /* clock period in picoseconds */
  1067. int clock; /* clock freq in MHz */
  1068. int cs;
  1069. u16 mem_speed = ddr3_cfg->mem_speed;
  1070. mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1071. if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
  1072. mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1073. /* Limit mem_speed for MX6D/MX6Q */
  1074. if (is_mx6dq() || is_mx6dqp()) {
  1075. if (mem_speed > 1066)
  1076. mem_speed = 1066; /* 1066 MT/s */
  1077. tcwl = 4;
  1078. }
  1079. /* Limit mem_speed for MX6S/MX6DL */
  1080. else {
  1081. if (mem_speed > 800)
  1082. mem_speed = 800; /* 800 MT/s */
  1083. tcwl = 3;
  1084. }
  1085. clock = mem_speed / 2;
  1086. /*
  1087. * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
  1088. * up to 528 MHz, so reduce the clock to fit chip specs
  1089. */
  1090. if (is_mx6dq() || is_mx6dqp()) {
  1091. if (clock > 528)
  1092. clock = 528; /* 528 MHz */
  1093. }
  1094. clkper = (1000 * 1000) / clock; /* pico seconds */
  1095. todtlon = tcwl;
  1096. taxpd = tcwl;
  1097. tanpd = tcwl;
  1098. switch (ddr3_cfg->density) {
  1099. case 1: /* 1Gb per chip */
  1100. trfc = DIV_ROUND_UP(110000, clkper) - 1;
  1101. txs = DIV_ROUND_UP(120000, clkper) - 1;
  1102. break;
  1103. case 2: /* 2Gb per chip */
  1104. trfc = DIV_ROUND_UP(160000, clkper) - 1;
  1105. txs = DIV_ROUND_UP(170000, clkper) - 1;
  1106. break;
  1107. case 4: /* 4Gb per chip */
  1108. trfc = DIV_ROUND_UP(260000, clkper) - 1;
  1109. txs = DIV_ROUND_UP(270000, clkper) - 1;
  1110. break;
  1111. case 8: /* 8Gb per chip */
  1112. trfc = DIV_ROUND_UP(350000, clkper) - 1;
  1113. txs = DIV_ROUND_UP(360000, clkper) - 1;
  1114. break;
  1115. default:
  1116. /* invalid density */
  1117. puts("invalid chip density\n");
  1118. hang();
  1119. break;
  1120. }
  1121. txpr = txs;
  1122. switch (mem_speed) {
  1123. case 800:
  1124. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1125. tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1126. if (ddr3_cfg->pagesz == 1) {
  1127. tfaw = DIV_ROUND_UP(40000, clkper) - 1;
  1128. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1129. } else {
  1130. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1131. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1132. }
  1133. break;
  1134. case 1066:
  1135. txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
  1136. tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
  1137. if (ddr3_cfg->pagesz == 1) {
  1138. tfaw = DIV_ROUND_UP(37500, clkper) - 1;
  1139. trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
  1140. } else {
  1141. tfaw = DIV_ROUND_UP(50000, clkper) - 1;
  1142. trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
  1143. }
  1144. break;
  1145. default:
  1146. puts("invalid memory speed\n");
  1147. hang();
  1148. break;
  1149. }
  1150. txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
  1151. tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
  1152. taonpd = DIV_ROUND_UP(2000, clkper) - 1;
  1153. tcksrx = tcksre;
  1154. taofpd = taonpd;
  1155. twr = DIV_ROUND_UP(15000, clkper) - 1;
  1156. tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
  1157. trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
  1158. tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
  1159. tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
  1160. trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
  1161. twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
  1162. trcd = trp;
  1163. trtp = twtr;
  1164. cs0_end = 4 * sysinfo->cs_density - 1;
  1165. debug("density:%d Gb (%d Gb per chip)\n",
  1166. sysinfo->cs_density, ddr3_cfg->density);
  1167. debug("clock: %dMHz (%d ps)\n", clock, clkper);
  1168. debug("memspd:%d\n", mem_speed);
  1169. debug("tcke=%d\n", tcke);
  1170. debug("tcksrx=%d\n", tcksrx);
  1171. debug("tcksre=%d\n", tcksre);
  1172. debug("taofpd=%d\n", taofpd);
  1173. debug("taonpd=%d\n", taonpd);
  1174. debug("todtlon=%d\n", todtlon);
  1175. debug("tanpd=%d\n", tanpd);
  1176. debug("taxpd=%d\n", taxpd);
  1177. debug("trfc=%d\n", trfc);
  1178. debug("txs=%d\n", txs);
  1179. debug("txp=%d\n", txp);
  1180. debug("txpdll=%d\n", txpdll);
  1181. debug("tfaw=%d\n", tfaw);
  1182. debug("tcl=%d\n", tcl);
  1183. debug("trcd=%d\n", trcd);
  1184. debug("trp=%d\n", trp);
  1185. debug("trc=%d\n", trc);
  1186. debug("tras=%d\n", tras);
  1187. debug("twr=%d\n", twr);
  1188. debug("tmrd=%d\n", tmrd);
  1189. debug("tcwl=%d\n", tcwl);
  1190. debug("tdllk=%d\n", tdllk);
  1191. debug("trtp=%d\n", trtp);
  1192. debug("twtr=%d\n", twtr);
  1193. debug("trrd=%d\n", trrd);
  1194. debug("txpr=%d\n", txpr);
  1195. debug("cs0_end=%d\n", cs0_end);
  1196. debug("ncs=%d\n", sysinfo->ncs);
  1197. debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
  1198. debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
  1199. debug("SRT=%d\n", ddr3_cfg->SRT);
  1200. debug("twr=%d\n", twr);
  1201. /*
  1202. * board-specific configuration:
  1203. * These values are determined empirically and vary per board layout
  1204. * see:
  1205. * appnote, ddr3 spreadsheet
  1206. */
  1207. mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
  1208. mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
  1209. mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
  1210. mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
  1211. mmdc0->mprddlctl = calib->p0_mprddlctl;
  1212. mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
  1213. if (sysinfo->dsize > 1) {
  1214. MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
  1215. MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
  1216. MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
  1217. MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
  1218. MMDC1(mprddlctl, calib->p1_mprddlctl);
  1219. MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
  1220. }
  1221. /* Read data DQ Byte0-3 delay */
  1222. mmdc0->mprddqby0dl = 0x33333333;
  1223. mmdc0->mprddqby1dl = 0x33333333;
  1224. if (sysinfo->dsize > 0) {
  1225. mmdc0->mprddqby2dl = 0x33333333;
  1226. mmdc0->mprddqby3dl = 0x33333333;
  1227. }
  1228. if (sysinfo->dsize > 1) {
  1229. MMDC1(mprddqby0dl, 0x33333333);
  1230. MMDC1(mprddqby1dl, 0x33333333);
  1231. MMDC1(mprddqby2dl, 0x33333333);
  1232. MMDC1(mprddqby3dl, 0x33333333);
  1233. }
  1234. /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
  1235. val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
  1236. mmdc0->mpodtctrl = val;
  1237. if (sysinfo->dsize > 1)
  1238. MMDC1(mpodtctrl, val);
  1239. /* complete calibration */
  1240. val = (1 << 11); /* Force measurement on delay-lines */
  1241. mmdc0->mpmur0 = val;
  1242. if (sysinfo->dsize > 1)
  1243. MMDC1(mpmur0, val);
  1244. /* Step 1: configuration request */
  1245. mmdc0->mdscr = (u32)(1 << 15); /* config request */
  1246. /* Step 2: Timing configuration */
  1247. mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
  1248. (txpdll << 9) | (tfaw << 4) | tcl;
  1249. mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
  1250. (tras << 16) | (1 << 15) /* trpa */ |
  1251. (twr << 9) | (tmrd << 5) | tcwl;
  1252. mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
  1253. mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
  1254. (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
  1255. mmdc0->mdasp = cs0_end; /* CS addressing */
  1256. /* Step 3: Configure DDR type */
  1257. mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
  1258. (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
  1259. (sysinfo->ralat << 6);
  1260. /* Step 4: Configure delay while leaving reset */
  1261. mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
  1262. (sysinfo->rst_to_cke << 0);
  1263. /* Step 5: Configure DDR physical parameters (density and burst len) */
  1264. coladdr = ddr3_cfg->coladdr;
  1265. if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
  1266. coladdr += 4;
  1267. else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
  1268. coladdr += 1;
  1269. mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
  1270. (coladdr - 9) << 20 | /* COL */
  1271. (1 << 19) | /* Burst Length = 8 for DDR3 */
  1272. (sysinfo->dsize << 16); /* DDR data bus size */
  1273. /* Step 6: Perform ZQ calibration */
  1274. val = 0xa1390001; /* one-time HW ZQ calib */
  1275. mmdc0->mpzqhwctrl = val;
  1276. if (sysinfo->dsize > 1)
  1277. MMDC1(mpzqhwctrl, val);
  1278. /* Step 7: Enable MMDC with desired chip select */
  1279. mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
  1280. ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
  1281. /* Step 8: Write Mode Registers to Init DDR3 devices */
  1282. for (cs = 0; cs < sysinfo->ncs; cs++) {
  1283. /* MR2 */
  1284. val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
  1285. ((tcwl - 3) & 3) << 3;
  1286. debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
  1287. mmdc0->mdscr = MR(val, 2, 3, cs);
  1288. /* MR3 */
  1289. debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
  1290. mmdc0->mdscr = MR(0, 3, 3, cs);
  1291. /* MR1 */
  1292. val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
  1293. ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
  1294. debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
  1295. mmdc0->mdscr = MR(val, 1, 3, cs);
  1296. /* MR0 */
  1297. val = ((tcl - 1) << 4) | /* CAS */
  1298. (1 << 8) | /* DLL Reset */
  1299. ((twr - 3) << 9) | /* Write Recovery */
  1300. (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
  1301. debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
  1302. mmdc0->mdscr = MR(val, 0, 3, cs);
  1303. /* ZQ calibration */
  1304. val = (1 << 10);
  1305. mmdc0->mdscr = MR(val, 0, 4, cs);
  1306. }
  1307. /* Step 10: Power down control and self-refresh */
  1308. mmdc0->mdpdc = (tcke & 0x7) << 16 |
  1309. 5 << 12 | /* PWDT_1: 256 cycles */
  1310. 5 << 8 | /* PWDT_0: 256 cycles */
  1311. 1 << 6 | /* BOTH_CS_PD */
  1312. (tcksrx & 0x7) << 3 |
  1313. (tcksre & 0x7);
  1314. if (!sysinfo->pd_fast_exit)
  1315. mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
  1316. mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
  1317. /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
  1318. val = 0xa1390003;
  1319. mmdc0->mpzqhwctrl = val;
  1320. if (sysinfo->dsize > 1)
  1321. MMDC1(mpzqhwctrl, val);
  1322. /* Step 12: Configure and activate periodic refresh */
  1323. mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
  1324. /* Step 13: Deassert config request - init complete */
  1325. mmdc0->mdscr = 0x00000000;
  1326. /* wait for auto-ZQ calibration to complete */
  1327. mdelay(1);
  1328. }
  1329. void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
  1330. struct mx6_mmdc_calibration *calib)
  1331. {
  1332. struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
  1333. struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
  1334. calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
  1335. calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
  1336. calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
  1337. calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
  1338. calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
  1339. calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
  1340. if (sysinfo->dsize == 2) {
  1341. calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
  1342. calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
  1343. calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
  1344. calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
  1345. calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
  1346. calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
  1347. }
  1348. }
  1349. void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  1350. const struct mx6_mmdc_calibration *calib,
  1351. const void *ddr_cfg)
  1352. {
  1353. if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
  1354. mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
  1355. } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
  1356. mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
  1357. } else {
  1358. puts("Unsupported ddr type\n");
  1359. hang();
  1360. }
  1361. }