mmu.h 3.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. */
  6. #ifndef _ASM_ARMV8_MMU_H_
  7. #define _ASM_ARMV8_MMU_H_
  8. #include <hang.h>
  9. #include <linux/const.h>
  10. /*
  11. * block/section address mask and size definitions.
  12. */
  13. /* PAGE_SHIFT determines the page size */
  14. #undef PAGE_SIZE
  15. #define PAGE_SHIFT 12
  16. #define PAGE_SIZE (1 << PAGE_SHIFT)
  17. #define PAGE_MASK (~(PAGE_SIZE - 1))
  18. /***************************************************************/
  19. /*
  20. * Memory types
  21. */
  22. #define MT_DEVICE_NGNRNE 0
  23. #define MT_DEVICE_NGNRE 1
  24. #define MT_DEVICE_GRE 2
  25. #define MT_NORMAL_NC 3
  26. #define MT_NORMAL 4
  27. #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
  28. (0x04 << (MT_DEVICE_NGNRE * 8)) | \
  29. (0x0c << (MT_DEVICE_GRE * 8)) | \
  30. (0x44 << (MT_NORMAL_NC * 8)) | \
  31. (UL(0xff) << (MT_NORMAL * 8)))
  32. /*
  33. * Hardware page table definitions.
  34. *
  35. */
  36. #define PTE_TYPE_MASK (3 << 0)
  37. #define PTE_TYPE_FAULT (0 << 0)
  38. #define PTE_TYPE_TABLE (3 << 0)
  39. #define PTE_TYPE_PAGE (3 << 0)
  40. #define PTE_TYPE_BLOCK (1 << 0)
  41. #define PTE_TYPE_VALID (1 << 0)
  42. #define PTE_TABLE_PXN (1UL << 59)
  43. #define PTE_TABLE_XN (1UL << 60)
  44. #define PTE_TABLE_AP (1UL << 61)
  45. #define PTE_TABLE_NS (1UL << 63)
  46. /*
  47. * Block
  48. */
  49. #define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
  50. #define PTE_BLOCK_NS (1 << 5)
  51. #define PTE_BLOCK_NON_SHARE (0 << 8)
  52. #define PTE_BLOCK_OUTER_SHARE (2 << 8)
  53. #define PTE_BLOCK_INNER_SHARE (3 << 8)
  54. #define PTE_BLOCK_AF (1 << 10)
  55. #define PTE_BLOCK_NG (1 << 11)
  56. #define PTE_BLOCK_PXN (UL(1) << 53)
  57. #define PTE_BLOCK_UXN (UL(1) << 54)
  58. /*
  59. * AttrIndx[2:0]
  60. */
  61. #define PMD_ATTRINDX(t) ((t) << 2)
  62. #define PMD_ATTRINDX_MASK (7 << 2)
  63. #define PMD_ATTRMASK (PTE_BLOCK_PXN | \
  64. PTE_BLOCK_UXN | \
  65. PMD_ATTRINDX_MASK | \
  66. PTE_TYPE_VALID)
  67. /*
  68. * TCR flags.
  69. */
  70. #define TCR_T0SZ(x) ((64 - (x)) << 0)
  71. #define TCR_IRGN_NC (0 << 8)
  72. #define TCR_IRGN_WBWA (1 << 8)
  73. #define TCR_IRGN_WT (2 << 8)
  74. #define TCR_IRGN_WBNWA (3 << 8)
  75. #define TCR_IRGN_MASK (3 << 8)
  76. #define TCR_ORGN_NC (0 << 10)
  77. #define TCR_ORGN_WBWA (1 << 10)
  78. #define TCR_ORGN_WT (2 << 10)
  79. #define TCR_ORGN_WBNWA (3 << 10)
  80. #define TCR_ORGN_MASK (3 << 10)
  81. #define TCR_SHARED_NON (0 << 12)
  82. #define TCR_SHARED_OUTER (2 << 12)
  83. #define TCR_SHARED_INNER (3 << 12)
  84. #define TCR_TG0_4K (0 << 14)
  85. #define TCR_TG0_64K (1 << 14)
  86. #define TCR_TG0_16K (2 << 14)
  87. #define TCR_EPD1_DISABLE (1 << 23)
  88. #define TCR_EL1_RSVD (1 << 31)
  89. #define TCR_EL2_RSVD (1 << 31 | 1 << 23)
  90. #define TCR_EL3_RSVD (1 << 31 | 1 << 23)
  91. #ifndef __ASSEMBLY__
  92. static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
  93. {
  94. asm volatile("dsb sy");
  95. if (el == 1) {
  96. asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
  97. asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
  98. asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
  99. } else if (el == 2) {
  100. asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
  101. asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
  102. asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
  103. } else if (el == 3) {
  104. asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
  105. asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
  106. asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
  107. } else {
  108. hang();
  109. }
  110. asm volatile("isb");
  111. }
  112. struct mm_region {
  113. u64 virt;
  114. u64 phys;
  115. u64 size;
  116. u64 attrs;
  117. };
  118. extern struct mm_region *mem_map;
  119. void setup_pgtables(void);
  120. u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
  121. #endif
  122. #endif /* _ASM_ARMV8_MMU_H_ */