cache_v8.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. *
  6. * (C) Copyright 2016
  7. * Alexander Graf <agraf@suse.de>
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <hang.h>
  12. #include <asm/system.h>
  13. #include <asm/armv8/mmu.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  16. /*
  17. * With 4k page granule, a virtual address is split into 4 lookup parts
  18. * spanning 9 bits each:
  19. *
  20. * _______________________________________________
  21. * | | | | | | |
  22. * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
  23. * |_______|_______|_______|_______|_______|_______|
  24. * 63-48 47-39 38-30 29-21 20-12 11-00
  25. *
  26. * mask page size
  27. *
  28. * Lv0: FF8000000000 --
  29. * Lv1: 7FC0000000 1G
  30. * Lv2: 3FE00000 2M
  31. * Lv3: 1FF000 4K
  32. * off: FFF
  33. */
  34. u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
  35. {
  36. u64 max_addr = 0;
  37. u64 ips, va_bits;
  38. u64 tcr;
  39. int i;
  40. /* Find the largest address we need to support */
  41. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  42. max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
  43. /* Calculate the maximum physical (and thus virtual) address */
  44. if (max_addr > (1ULL << 44)) {
  45. ips = 5;
  46. va_bits = 48;
  47. } else if (max_addr > (1ULL << 42)) {
  48. ips = 4;
  49. va_bits = 44;
  50. } else if (max_addr > (1ULL << 40)) {
  51. ips = 3;
  52. va_bits = 42;
  53. } else if (max_addr > (1ULL << 36)) {
  54. ips = 2;
  55. va_bits = 40;
  56. } else if (max_addr > (1ULL << 32)) {
  57. ips = 1;
  58. va_bits = 36;
  59. } else {
  60. ips = 0;
  61. va_bits = 32;
  62. }
  63. if (el == 1) {
  64. tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
  65. } else if (el == 2) {
  66. tcr = TCR_EL2_RSVD | (ips << 16);
  67. } else {
  68. tcr = TCR_EL3_RSVD | (ips << 16);
  69. }
  70. /* PTWs cacheable, inner/outer WBWA and inner shareable */
  71. tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
  72. tcr |= TCR_T0SZ(va_bits);
  73. if (pips)
  74. *pips = ips;
  75. if (pva_bits)
  76. *pva_bits = va_bits;
  77. return tcr;
  78. }
  79. #define MAX_PTE_ENTRIES 512
  80. static int pte_type(u64 *pte)
  81. {
  82. return *pte & PTE_TYPE_MASK;
  83. }
  84. /* Returns the LSB number for a PTE on level <level> */
  85. static int level2shift(int level)
  86. {
  87. /* Page is 12 bits wide, every level translates 9 bits */
  88. return (12 + 9 * (3 - level));
  89. }
  90. static u64 *find_pte(u64 addr, int level)
  91. {
  92. int start_level = 0;
  93. u64 *pte;
  94. u64 idx;
  95. u64 va_bits;
  96. int i;
  97. debug("addr=%llx level=%d\n", addr, level);
  98. get_tcr(0, NULL, &va_bits);
  99. if (va_bits < 39)
  100. start_level = 1;
  101. if (level < start_level)
  102. return NULL;
  103. /* Walk through all page table levels to find our PTE */
  104. pte = (u64*)gd->arch.tlb_addr;
  105. for (i = start_level; i < 4; i++) {
  106. idx = (addr >> level2shift(i)) & 0x1FF;
  107. pte += idx;
  108. debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
  109. /* Found it */
  110. if (i == level)
  111. return pte;
  112. /* PTE is no table (either invalid or block), can't traverse */
  113. if (pte_type(pte) != PTE_TYPE_TABLE)
  114. return NULL;
  115. /* Off to the next level */
  116. pte = (u64*)(*pte & 0x0000fffffffff000ULL);
  117. }
  118. /* Should never reach here */
  119. return NULL;
  120. }
  121. /* Returns and creates a new full table (512 entries) */
  122. static u64 *create_table(void)
  123. {
  124. u64 *new_table = (u64*)gd->arch.tlb_fillptr;
  125. u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
  126. /* Allocate MAX_PTE_ENTRIES pte entries */
  127. gd->arch.tlb_fillptr += pt_len;
  128. if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
  129. panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
  130. "Please increase the size in get_page_table_size()",
  131. gd->arch.tlb_fillptr - gd->arch.tlb_addr,
  132. gd->arch.tlb_size);
  133. /* Mark all entries as invalid */
  134. memset(new_table, 0, pt_len);
  135. return new_table;
  136. }
  137. static void set_pte_table(u64 *pte, u64 *table)
  138. {
  139. /* Point *pte to the new table */
  140. debug("Setting %p to addr=%p\n", pte, table);
  141. *pte = PTE_TYPE_TABLE | (ulong)table;
  142. }
  143. /* Splits a block PTE into table with subpages spanning the old block */
  144. static void split_block(u64 *pte, int level)
  145. {
  146. u64 old_pte = *pte;
  147. u64 *new_table;
  148. u64 i = 0;
  149. /* level describes the parent level, we need the child ones */
  150. int levelshift = level2shift(level + 1);
  151. if (pte_type(pte) != PTE_TYPE_BLOCK)
  152. panic("PTE %p (%llx) is not a block. Some driver code wants to "
  153. "modify dcache settings for an range not covered in "
  154. "mem_map.", pte, old_pte);
  155. new_table = create_table();
  156. debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
  157. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  158. new_table[i] = old_pte | (i << levelshift);
  159. /* Level 3 block PTEs have the table type */
  160. if ((level + 1) == 3)
  161. new_table[i] |= PTE_TYPE_TABLE;
  162. debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
  163. }
  164. /* Set the new table into effect */
  165. set_pte_table(pte, new_table);
  166. }
  167. /* Add one mm_region map entry to the page tables */
  168. static void add_map(struct mm_region *map)
  169. {
  170. u64 *pte;
  171. u64 virt = map->virt;
  172. u64 phys = map->phys;
  173. u64 size = map->size;
  174. u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
  175. u64 blocksize;
  176. int level;
  177. u64 *new_table;
  178. while (size) {
  179. pte = find_pte(virt, 0);
  180. if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
  181. debug("Creating table for virt 0x%llx\n", virt);
  182. new_table = create_table();
  183. set_pte_table(pte, new_table);
  184. }
  185. for (level = 1; level < 4; level++) {
  186. pte = find_pte(virt, level);
  187. if (!pte)
  188. panic("pte not found\n");
  189. blocksize = 1ULL << level2shift(level);
  190. debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
  191. virt, size, blocksize);
  192. if (size >= blocksize && !(virt & (blocksize - 1))) {
  193. /* Page fits, create block PTE */
  194. debug("Setting PTE %p to block virt=%llx\n",
  195. pte, virt);
  196. if (level == 3)
  197. *pte = phys | attrs | PTE_TYPE_PAGE;
  198. else
  199. *pte = phys | attrs;
  200. virt += blocksize;
  201. phys += blocksize;
  202. size -= blocksize;
  203. break;
  204. } else if (pte_type(pte) == PTE_TYPE_FAULT) {
  205. /* Page doesn't fit, create subpages */
  206. debug("Creating subtable for virt 0x%llx blksize=%llx\n",
  207. virt, blocksize);
  208. new_table = create_table();
  209. set_pte_table(pte, new_table);
  210. } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
  211. debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
  212. virt, blocksize);
  213. split_block(pte, level);
  214. }
  215. }
  216. }
  217. }
  218. enum pte_type {
  219. PTE_INVAL,
  220. PTE_BLOCK,
  221. PTE_LEVEL,
  222. };
  223. /*
  224. * This is a recursively called function to count the number of
  225. * page tables we need to cover a particular PTE range. If you
  226. * call this with level = -1 you basically get the full 48 bit
  227. * coverage.
  228. */
  229. static int count_required_pts(u64 addr, int level, u64 maxaddr)
  230. {
  231. int levelshift = level2shift(level);
  232. u64 levelsize = 1ULL << levelshift;
  233. u64 levelmask = levelsize - 1;
  234. u64 levelend = addr + levelsize;
  235. int r = 0;
  236. int i;
  237. enum pte_type pte_type = PTE_INVAL;
  238. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
  239. struct mm_region *map = &mem_map[i];
  240. u64 start = map->virt;
  241. u64 end = start + map->size;
  242. /* Check if the PTE would overlap with the map */
  243. if (max(addr, start) <= min(levelend, end)) {
  244. start = max(addr, start);
  245. end = min(levelend, end);
  246. /* We need a sub-pt for this level */
  247. if ((start & levelmask) || (end & levelmask)) {
  248. pte_type = PTE_LEVEL;
  249. break;
  250. }
  251. /* Lv0 can not do block PTEs, so do levels here too */
  252. if (level <= 0) {
  253. pte_type = PTE_LEVEL;
  254. break;
  255. }
  256. /* PTE is active, but fits into a block */
  257. pte_type = PTE_BLOCK;
  258. }
  259. }
  260. /*
  261. * Block PTEs at this level are already covered by the parent page
  262. * table, so we only need to count sub page tables.
  263. */
  264. if (pte_type == PTE_LEVEL) {
  265. int sublevel = level + 1;
  266. u64 sublevelsize = 1ULL << level2shift(sublevel);
  267. /* Account for the new sub page table ... */
  268. r = 1;
  269. /* ... and for all child page tables that one might have */
  270. for (i = 0; i < MAX_PTE_ENTRIES; i++) {
  271. r += count_required_pts(addr, sublevel, maxaddr);
  272. addr += sublevelsize;
  273. if (addr >= maxaddr) {
  274. /*
  275. * We reached the end of address space, no need
  276. * to look any further.
  277. */
  278. break;
  279. }
  280. }
  281. }
  282. return r;
  283. }
  284. /* Returns the estimated required size of all page tables */
  285. __weak u64 get_page_table_size(void)
  286. {
  287. u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
  288. u64 size = 0;
  289. u64 va_bits;
  290. int start_level = 0;
  291. get_tcr(0, NULL, &va_bits);
  292. if (va_bits < 39)
  293. start_level = 1;
  294. /* Account for all page tables we would need to cover our memory map */
  295. size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
  296. /*
  297. * We need to duplicate our page table once to have an emergency pt to
  298. * resort to when splitting page tables later on
  299. */
  300. size *= 2;
  301. /*
  302. * We may need to split page tables later on if dcache settings change,
  303. * so reserve up to 4 (random pick) page tables for that.
  304. */
  305. size += one_pt * 4;
  306. return size;
  307. }
  308. void setup_pgtables(void)
  309. {
  310. int i;
  311. if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
  312. panic("Page table pointer not setup.");
  313. /*
  314. * Allocate the first level we're on with invalidate entries.
  315. * If the starting level is 0 (va_bits >= 39), then this is our
  316. * Lv0 page table, otherwise it's the entry Lv1 page table.
  317. */
  318. create_table();
  319. /* Now add all MMU table entries one after another to the table */
  320. for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  321. add_map(&mem_map[i]);
  322. }
  323. static void setup_all_pgtables(void)
  324. {
  325. u64 tlb_addr = gd->arch.tlb_addr;
  326. u64 tlb_size = gd->arch.tlb_size;
  327. /* Reset the fill ptr */
  328. gd->arch.tlb_fillptr = tlb_addr;
  329. /* Create normal system page tables */
  330. setup_pgtables();
  331. /* Create emergency page tables */
  332. gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
  333. (uintptr_t)gd->arch.tlb_addr;
  334. gd->arch.tlb_addr = gd->arch.tlb_fillptr;
  335. setup_pgtables();
  336. gd->arch.tlb_emerg = gd->arch.tlb_addr;
  337. gd->arch.tlb_addr = tlb_addr;
  338. gd->arch.tlb_size = tlb_size;
  339. }
  340. /* to activate the MMU we need to set up virtual memory */
  341. __weak void mmu_setup(void)
  342. {
  343. int el;
  344. /* Set up page tables only once */
  345. if (!gd->arch.tlb_fillptr)
  346. setup_all_pgtables();
  347. el = current_el();
  348. set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
  349. MEMORY_ATTRIBUTES);
  350. /* enable the mmu */
  351. set_sctlr(get_sctlr() | CR_M);
  352. }
  353. /*
  354. * Performs a invalidation of the entire data cache at all levels
  355. */
  356. void invalidate_dcache_all(void)
  357. {
  358. __asm_invalidate_dcache_all();
  359. __asm_invalidate_l3_dcache();
  360. }
  361. /*
  362. * Performs a clean & invalidation of the entire data cache at all levels.
  363. * This function needs to be inline to avoid using stack.
  364. * __asm_flush_l3_dcache return status of timeout
  365. */
  366. inline void flush_dcache_all(void)
  367. {
  368. int ret;
  369. __asm_flush_dcache_all();
  370. ret = __asm_flush_l3_dcache();
  371. if (ret)
  372. debug("flushing dcache returns 0x%x\n", ret);
  373. else
  374. debug("flushing dcache successfully.\n");
  375. }
  376. #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
  377. /*
  378. * Invalidates range in all levels of D-cache/unified cache
  379. */
  380. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  381. {
  382. __asm_invalidate_dcache_range(start, stop);
  383. }
  384. /*
  385. * Flush range(clean & invalidate) from all levels of D-cache/unified cache
  386. */
  387. void flush_dcache_range(unsigned long start, unsigned long stop)
  388. {
  389. __asm_flush_dcache_range(start, stop);
  390. }
  391. #else
  392. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  393. {
  394. }
  395. void flush_dcache_range(unsigned long start, unsigned long stop)
  396. {
  397. }
  398. #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
  399. void dcache_enable(void)
  400. {
  401. /* The data cache is not active unless the mmu is enabled */
  402. if (!(get_sctlr() & CR_M)) {
  403. invalidate_dcache_all();
  404. __asm_invalidate_tlb_all();
  405. mmu_setup();
  406. }
  407. set_sctlr(get_sctlr() | CR_C);
  408. }
  409. void dcache_disable(void)
  410. {
  411. uint32_t sctlr;
  412. sctlr = get_sctlr();
  413. /* if cache isn't enabled no need to disable */
  414. if (!(sctlr & CR_C))
  415. return;
  416. set_sctlr(sctlr & ~(CR_C|CR_M));
  417. flush_dcache_all();
  418. __asm_invalidate_tlb_all();
  419. }
  420. int dcache_status(void)
  421. {
  422. return (get_sctlr() & CR_C) != 0;
  423. }
  424. u64 *__weak arch_get_page_table(void) {
  425. puts("No page table offset defined\n");
  426. return NULL;
  427. }
  428. static bool is_aligned(u64 addr, u64 size, u64 align)
  429. {
  430. return !(addr & (align - 1)) && !(size & (align - 1));
  431. }
  432. /* Use flag to indicate if attrs has more than d-cache attributes */
  433. static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
  434. {
  435. int levelshift = level2shift(level);
  436. u64 levelsize = 1ULL << levelshift;
  437. u64 *pte = find_pte(start, level);
  438. /* Can we can just modify the current level block PTE? */
  439. if (is_aligned(start, size, levelsize)) {
  440. if (flag) {
  441. *pte &= ~PMD_ATTRMASK;
  442. *pte |= attrs & PMD_ATTRMASK;
  443. } else {
  444. *pte &= ~PMD_ATTRINDX_MASK;
  445. *pte |= attrs & PMD_ATTRINDX_MASK;
  446. }
  447. debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
  448. return levelsize;
  449. }
  450. /* Unaligned or doesn't fit, maybe split block into table */
  451. debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
  452. /* Maybe we need to split the block into a table */
  453. if (pte_type(pte) == PTE_TYPE_BLOCK)
  454. split_block(pte, level);
  455. /* And then double-check it became a table or already is one */
  456. if (pte_type(pte) != PTE_TYPE_TABLE)
  457. panic("PTE %p (%llx) for addr=%llx should be a table",
  458. pte, *pte, start);
  459. /* Roll on to the next page table level */
  460. return 0;
  461. }
  462. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  463. enum dcache_option option)
  464. {
  465. u64 attrs = PMD_ATTRINDX(option);
  466. u64 real_start = start;
  467. u64 real_size = size;
  468. debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
  469. if (!gd->arch.tlb_emerg)
  470. panic("Emergency page table not setup.");
  471. /*
  472. * We can not modify page tables that we're currently running on,
  473. * so we first need to switch to the "emergency" page tables where
  474. * we can safely modify our primary page tables and then switch back
  475. */
  476. __asm_switch_ttbr(gd->arch.tlb_emerg);
  477. /*
  478. * Loop through the address range until we find a page granule that fits
  479. * our alignment constraints, then set it to the new cache attributes
  480. */
  481. while (size > 0) {
  482. int level;
  483. u64 r;
  484. for (level = 1; level < 4; level++) {
  485. /* Set d-cache attributes only */
  486. r = set_one_region(start, size, attrs, false, level);
  487. if (r) {
  488. /* PTE successfully replaced */
  489. size -= r;
  490. start += r;
  491. break;
  492. }
  493. }
  494. }
  495. /* We're done modifying page tables, switch back to our primary ones */
  496. __asm_switch_ttbr(gd->arch.tlb_addr);
  497. /*
  498. * Make sure there's nothing stale in dcache for a region that might
  499. * have caches off now
  500. */
  501. flush_dcache_range(real_start, real_start + real_size);
  502. }
  503. /*
  504. * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
  505. * The procecess is break-before-make. The target region will be marked as
  506. * invalid during the process of changing.
  507. */
  508. void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
  509. {
  510. int level;
  511. u64 r, size, start;
  512. start = addr;
  513. size = siz;
  514. /*
  515. * Loop through the address range until we find a page granule that fits
  516. * our alignment constraints, then set it to "invalid".
  517. */
  518. while (size > 0) {
  519. for (level = 1; level < 4; level++) {
  520. /* Set PTE to fault */
  521. r = set_one_region(start, size, PTE_TYPE_FAULT, true,
  522. level);
  523. if (r) {
  524. /* PTE successfully invalidated */
  525. size -= r;
  526. start += r;
  527. break;
  528. }
  529. }
  530. }
  531. flush_dcache_range(gd->arch.tlb_addr,
  532. gd->arch.tlb_addr + gd->arch.tlb_size);
  533. __asm_invalidate_tlb_all();
  534. /*
  535. * Loop through the address range until we find a page granule that fits
  536. * our alignment constraints, then set it to the new cache attributes
  537. */
  538. start = addr;
  539. size = siz;
  540. while (size > 0) {
  541. for (level = 1; level < 4; level++) {
  542. /* Set PTE to new attributes */
  543. r = set_one_region(start, size, attrs, true, level);
  544. if (r) {
  545. /* PTE successfully updated */
  546. size -= r;
  547. start += r;
  548. break;
  549. }
  550. }
  551. }
  552. flush_dcache_range(gd->arch.tlb_addr,
  553. gd->arch.tlb_addr + gd->arch.tlb_size);
  554. __asm_invalidate_tlb_all();
  555. }
  556. #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  557. /*
  558. * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
  559. * running however really wants to have dcache and the MMU active. Check that
  560. * everything is sane and give the developer a hint if it isn't.
  561. */
  562. #ifndef CONFIG_SPL_BUILD
  563. #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
  564. #endif
  565. void invalidate_dcache_all(void)
  566. {
  567. }
  568. void flush_dcache_all(void)
  569. {
  570. }
  571. void dcache_enable(void)
  572. {
  573. }
  574. void dcache_disable(void)
  575. {
  576. }
  577. int dcache_status(void)
  578. {
  579. return 0;
  580. }
  581. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  582. enum dcache_option option)
  583. {
  584. }
  585. #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  586. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  587. void icache_enable(void)
  588. {
  589. invalidate_icache_all();
  590. set_sctlr(get_sctlr() | CR_I);
  591. }
  592. void icache_disable(void)
  593. {
  594. set_sctlr(get_sctlr() & ~CR_I);
  595. }
  596. int icache_status(void)
  597. {
  598. return (get_sctlr() & CR_I) != 0;
  599. }
  600. void invalidate_icache_all(void)
  601. {
  602. __asm_invalidate_icache_all();
  603. __asm_invalidate_l3_icache();
  604. }
  605. #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  606. void icache_enable(void)
  607. {
  608. }
  609. void icache_disable(void)
  610. {
  611. }
  612. int icache_status(void)
  613. {
  614. return 0;
  615. }
  616. void invalidate_icache_all(void)
  617. {
  618. }
  619. #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
  620. /*
  621. * Enable dCache & iCache, whether cache is actually enabled
  622. * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
  623. */
  624. void __weak enable_caches(void)
  625. {
  626. icache_enable();
  627. dcache_enable();
  628. }