spl_power_init.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 Boot PMIC init
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <config.h>
  10. #include <hang.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include "mxs_init.h"
  14. #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
  15. #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
  16. POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
  17. #else
  18. #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
  19. POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
  20. #endif
  21. /**
  22. * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  23. *
  24. * This function switches the CPU core clock from PLL to 24MHz XTAL
  25. * oscilator. This is necessary if the PLL is being reconfigured to
  26. * prevent crash of the CPU core.
  27. */
  28. static void mxs_power_clock2xtal(void)
  29. {
  30. struct mxs_clkctrl_regs *clkctrl_regs =
  31. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  32. debug("SPL: Switching CPU clock to 24MHz XTAL\n");
  33. /* Set XTAL as CPU reference clock */
  34. writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  35. &clkctrl_regs->hw_clkctrl_clkseq_set);
  36. }
  37. /**
  38. * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  39. *
  40. * This function switches the CPU core clock from 24MHz XTAL oscilator
  41. * to PLL. This can only be called once the PLL has re-locked and once
  42. * the PLL is stable after reconfiguration.
  43. */
  44. static void mxs_power_clock2pll(void)
  45. {
  46. struct mxs_clkctrl_regs *clkctrl_regs =
  47. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  48. debug("SPL: Switching CPU core clock source to PLL\n");
  49. /*
  50. * TODO: Are we really? It looks like we turn on PLL0, but we then
  51. * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
  52. * set by mxs_power_clock2xtal()). Clearing this bit here seems to
  53. * introduce some instability (causing the CPU core to hang). Maybe
  54. * we aren't giving PLL0 enough time to stabilise?
  55. */
  56. setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
  57. CLKCTRL_PLL0CTRL0_POWER);
  58. early_delay(100);
  59. /*
  60. * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
  61. * wait on the PLL0 LOCK bit?
  62. */
  63. setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
  64. CLKCTRL_CLKSEQ_BYPASS_CPU);
  65. }
  66. /**
  67. * mxs_power_set_auto_restart() - Set the auto-restart bit
  68. *
  69. * This function ungates the RTC block and sets the AUTO_RESTART
  70. * bit to work around a design bug on MX28EVK Rev. A .
  71. */
  72. static void mxs_power_set_auto_restart(void)
  73. {
  74. struct mxs_rtc_regs *rtc_regs =
  75. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  76. debug("SPL: Setting auto-restart bit\n");
  77. writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
  78. while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
  79. ;
  80. writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
  81. while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
  82. ;
  83. /* Do nothing if flag already set */
  84. if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
  85. return;
  86. while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
  87. ;
  88. setbits_le32(&rtc_regs->hw_rtc_persistent0,
  89. RTC_PERSISTENT0_AUTO_RESTART);
  90. writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
  91. writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
  92. while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
  93. ;
  94. while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
  95. ;
  96. }
  97. /**
  98. * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
  99. *
  100. * This function configures the VDDIO, VDDA and VDDD linear regulators output
  101. * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
  102. * converter. This is the recommended setting for the case where we use both
  103. * linear regulators and DC-DC converter to power the VDDIO rail.
  104. */
  105. static void mxs_power_set_linreg(void)
  106. {
  107. struct mxs_power_regs *power_regs =
  108. (struct mxs_power_regs *)MXS_POWER_BASE;
  109. /* Set linear regulator 25mV below switching converter */
  110. debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
  111. clrsetbits_le32(&power_regs->hw_power_vdddctrl,
  112. POWER_VDDDCTRL_LINREG_OFFSET_MASK,
  113. POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
  114. debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
  115. clrsetbits_le32(&power_regs->hw_power_vddactrl,
  116. POWER_VDDACTRL_LINREG_OFFSET_MASK,
  117. POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
  118. debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
  119. clrsetbits_le32(&power_regs->hw_power_vddioctrl,
  120. POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
  121. POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
  122. }
  123. /**
  124. * mxs_get_batt_volt() - Measure battery input voltage
  125. *
  126. * This function retrieves the battery input voltage and returns it.
  127. */
  128. static int mxs_get_batt_volt(void)
  129. {
  130. struct mxs_power_regs *power_regs =
  131. (struct mxs_power_regs *)MXS_POWER_BASE;
  132. uint32_t volt = readl(&power_regs->hw_power_battmonitor);
  133. volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
  134. volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
  135. volt *= 8;
  136. debug("SPL: Battery Voltage = %dmV\n", volt);
  137. return volt;
  138. }
  139. /**
  140. * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
  141. *
  142. * This function checks if the battery input voltage is higher than 3.6V and
  143. * therefore allows the system to successfully boot using this power source.
  144. */
  145. static int mxs_is_batt_ready(void)
  146. {
  147. return (mxs_get_batt_volt() >= 3600);
  148. }
  149. /**
  150. * mxs_is_batt_good() - Test if battery is operational at all
  151. *
  152. * This function starts recharging the battery and tests if the input current
  153. * provided by the 5V input recharging the battery is also sufficient to power
  154. * the DC-DC converter.
  155. */
  156. static int mxs_is_batt_good(void)
  157. {
  158. struct mxs_power_regs *power_regs =
  159. (struct mxs_power_regs *)MXS_POWER_BASE;
  160. uint32_t volt = mxs_get_batt_volt();
  161. if ((volt >= 2400) && (volt <= 4300)) {
  162. debug("SPL: Battery is good\n");
  163. return 1;
  164. }
  165. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  166. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  167. 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  168. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  169. &power_regs->hw_power_5vctrl_clr);
  170. clrsetbits_le32(&power_regs->hw_power_charge,
  171. POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
  172. POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
  173. writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
  174. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  175. &power_regs->hw_power_5vctrl_clr);
  176. early_delay(500000);
  177. volt = mxs_get_batt_volt();
  178. if (volt >= 3500) {
  179. debug("SPL: Battery Voltage too high\n");
  180. return 0;
  181. }
  182. if (volt >= 2400) {
  183. debug("SPL: Battery is good\n");
  184. return 1;
  185. }
  186. writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
  187. &power_regs->hw_power_charge_clr);
  188. writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
  189. debug("SPL: Battery Voltage too low\n");
  190. return 0;
  191. }
  192. /**
  193. * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
  194. *
  195. * This function enables the 5V detection comparator and sets the 5V valid
  196. * threshold to 4.4V . We use 4.4V threshold here to make sure that even
  197. * under high load, the voltage drop on the 5V input won't be so critical
  198. * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
  199. * converter and thus making the system crash.
  200. */
  201. static void mxs_power_setup_5v_detect(void)
  202. {
  203. struct mxs_power_regs *power_regs =
  204. (struct mxs_power_regs *)MXS_POWER_BASE;
  205. /* Start 5V detection */
  206. debug("SPL: Starting 5V input detection comparator\n");
  207. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  208. POWER_5VCTRL_VBUSVALID_TRSH_MASK,
  209. POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
  210. POWER_5VCTRL_PWRUP_VBUS_CMPS);
  211. }
  212. /**
  213. * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters
  214. * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock
  215. *
  216. * This function configures and then enables an alternative PLL clock source
  217. * for the DC-DC converters.
  218. */
  219. void mxs_power_switch_dcdc_clocksource(uint32_t freqsel)
  220. {
  221. struct mxs_power_regs *power_regs =
  222. (struct mxs_power_regs *)MXS_POWER_BASE;
  223. /* Select clocksource for DC-DC converters */
  224. clrsetbits_le32(&power_regs->hw_power_misc,
  225. POWER_MISC_FREQSEL_MASK,
  226. freqsel);
  227. setbits_le32(&power_regs->hw_power_misc,
  228. POWER_MISC_SEL_PLLCLK);
  229. }
  230. /**
  231. * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters
  232. *
  233. * Normally, there is no need to switch DC-DC clocksource. This is the reason,
  234. * why this function is a stub and does nothing. However, boards can implement
  235. * this function when required and call mxs_power_switch_dcdc_clocksource() to
  236. * switch to an alternative clock source.
  237. */
  238. __weak void mxs_power_setup_dcdc_clocksource(void)
  239. {
  240. debug("SPL: Using default DC-DC clocksource\n");
  241. }
  242. /**
  243. * mxs_src_power_init() - Preconfigure the power block
  244. *
  245. * This function configures reasonable values for the DC-DC control loop
  246. * and battery monitor.
  247. */
  248. static void mxs_src_power_init(void)
  249. {
  250. struct mxs_power_regs *power_regs =
  251. (struct mxs_power_regs *)MXS_POWER_BASE;
  252. debug("SPL: Pre-Configuring power block\n");
  253. /* Improve efficieny and reduce transient ripple */
  254. writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
  255. POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
  256. clrsetbits_le32(&power_regs->hw_power_dclimits,
  257. POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
  258. 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
  259. setbits_le32(&power_regs->hw_power_battmonitor,
  260. POWER_BATTMONITOR_EN_BATADJ);
  261. /* Increase the RCSCALE level for quick DCDC response to dynamic load */
  262. clrsetbits_le32(&power_regs->hw_power_loopctrl,
  263. POWER_LOOPCTRL_EN_RCSCALE_MASK,
  264. POWER_LOOPCTRL_RCSCALE_THRESH |
  265. POWER_LOOPCTRL_EN_RCSCALE_8X);
  266. clrsetbits_le32(&power_regs->hw_power_minpwr,
  267. POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
  268. /* 5V to battery handoff ... FIXME */
  269. setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  270. early_delay(30);
  271. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  272. }
  273. /**
  274. * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
  275. *
  276. * This function configures the necessary parameters for the 4P2 linear
  277. * regulator to supply the DC-DC converter from 5V input.
  278. */
  279. static void mxs_power_init_4p2_params(void)
  280. {
  281. struct mxs_power_regs *power_regs =
  282. (struct mxs_power_regs *)MXS_POWER_BASE;
  283. debug("SPL: Configuring common 4P2 regulator params\n");
  284. /* Setup 4P2 parameters */
  285. clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  286. POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
  287. POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
  288. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  289. POWER_5VCTRL_HEADROOM_ADJ_MASK,
  290. 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
  291. clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  292. POWER_DCDC4P2_DROPOUT_CTRL_MASK,
  293. DCDC4P2_DROPOUT_CONFIG);
  294. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  295. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  296. 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  297. }
  298. /**
  299. * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
  300. * @xfer: Select if the input shall be enabled or disabled
  301. *
  302. * This function enables or disables the 4P2 input into the DC-DC converter.
  303. */
  304. static void mxs_enable_4p2_dcdc_input(int xfer)
  305. {
  306. struct mxs_power_regs *power_regs =
  307. (struct mxs_power_regs *)MXS_POWER_BASE;
  308. uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
  309. uint32_t prev_5v_brnout, prev_5v_droop;
  310. debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
  311. if (xfer && (readl(&power_regs->hw_power_5vctrl) &
  312. POWER_5VCTRL_ENABLE_DCDC)) {
  313. return;
  314. }
  315. prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
  316. POWER_5VCTRL_PWDN_5VBRNOUT;
  317. prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
  318. POWER_CTRL_ENIRQ_VDD5V_DROOP;
  319. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
  320. writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
  321. &power_regs->hw_power_reset);
  322. clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
  323. /*
  324. * Recording orignal values that will be modified temporarlily
  325. * to handle a chip bug. See chip errata for CQ ENGR00115837
  326. */
  327. tmp = readl(&power_regs->hw_power_5vctrl);
  328. vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
  329. vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
  330. pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
  331. /*
  332. * Disable mechanisms that get erroneously tripped by when setting
  333. * the DCDC4P2 EN_DCDC
  334. */
  335. clrbits_le32(&power_regs->hw_power_5vctrl,
  336. POWER_5VCTRL_VBUSVALID_5VDETECT |
  337. POWER_5VCTRL_VBUSVALID_TRSH_MASK);
  338. writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
  339. if (xfer) {
  340. setbits_le32(&power_regs->hw_power_5vctrl,
  341. POWER_5VCTRL_DCDC_XFER);
  342. early_delay(20);
  343. clrbits_le32(&power_regs->hw_power_5vctrl,
  344. POWER_5VCTRL_DCDC_XFER);
  345. setbits_le32(&power_regs->hw_power_5vctrl,
  346. POWER_5VCTRL_ENABLE_DCDC);
  347. } else {
  348. setbits_le32(&power_regs->hw_power_dcdc4p2,
  349. POWER_DCDC4P2_ENABLE_DCDC);
  350. }
  351. early_delay(25);
  352. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  353. POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
  354. if (vbus_5vdetect)
  355. writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
  356. if (!pwd_bo)
  357. clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
  358. while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
  359. writel(POWER_CTRL_VBUS_VALID_IRQ,
  360. &power_regs->hw_power_ctrl_clr);
  361. if (prev_5v_brnout) {
  362. writel(POWER_5VCTRL_PWDN_5VBRNOUT,
  363. &power_regs->hw_power_5vctrl_set);
  364. writel(POWER_RESET_UNLOCK_KEY,
  365. &power_regs->hw_power_reset);
  366. } else {
  367. writel(POWER_5VCTRL_PWDN_5VBRNOUT,
  368. &power_regs->hw_power_5vctrl_clr);
  369. writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
  370. &power_regs->hw_power_reset);
  371. }
  372. while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
  373. writel(POWER_CTRL_VDD5V_DROOP_IRQ,
  374. &power_regs->hw_power_ctrl_clr);
  375. if (prev_5v_droop)
  376. clrbits_le32(&power_regs->hw_power_ctrl,
  377. POWER_CTRL_ENIRQ_VDD5V_DROOP);
  378. else
  379. setbits_le32(&power_regs->hw_power_ctrl,
  380. POWER_CTRL_ENIRQ_VDD5V_DROOP);
  381. }
  382. /**
  383. * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
  384. *
  385. * This function enables the 4P2 regulator and switches the DC-DC converter
  386. * to use the 4P2 input.
  387. */
  388. static void mxs_power_init_4p2_regulator(void)
  389. {
  390. struct mxs_power_regs *power_regs =
  391. (struct mxs_power_regs *)MXS_POWER_BASE;
  392. uint32_t tmp, tmp2;
  393. debug("SPL: Enabling 4P2 regulator\n");
  394. setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
  395. writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
  396. writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  397. &power_regs->hw_power_5vctrl_clr);
  398. clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
  399. /* Power up the 4p2 rail and logic/control */
  400. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  401. &power_regs->hw_power_5vctrl_clr);
  402. /*
  403. * Start charging up the 4p2 capacitor. We ramp of this charge
  404. * gradually to avoid large inrush current from the 5V cable which can
  405. * cause transients/problems
  406. */
  407. debug("SPL: Charging 4P2 capacitor\n");
  408. mxs_enable_4p2_dcdc_input(0);
  409. if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
  410. /*
  411. * If we arrived here, we were unable to recover from mx23 chip
  412. * errata 5837. 4P2 is disabled and sufficient battery power is
  413. * not present. Exiting to not enable DCDC power during 5V
  414. * connected state.
  415. */
  416. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  417. POWER_DCDC4P2_ENABLE_DCDC);
  418. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  419. &power_regs->hw_power_5vctrl_set);
  420. debug("SPL: Unable to recover from mx23 errata 5837\n");
  421. hang();
  422. }
  423. /*
  424. * Here we set the 4p2 brownout level to something very close to 4.2V.
  425. * We then check the brownout status. If the brownout status is false,
  426. * the voltage is already close to the target voltage of 4.2V so we
  427. * can go ahead and set the 4P2 current limit to our max target limit.
  428. * If the brownout status is true, we need to ramp us the current limit
  429. * so that we don't cause large inrush current issues. We step up the
  430. * current limit until the brownout status is false or until we've
  431. * reached our maximum defined 4p2 current limit.
  432. */
  433. debug("SPL: Setting 4P2 brownout level\n");
  434. clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
  435. POWER_DCDC4P2_BO_MASK,
  436. 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
  437. if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
  438. setbits_le32(&power_regs->hw_power_5vctrl,
  439. 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  440. } else {
  441. tmp = (readl(&power_regs->hw_power_5vctrl) &
  442. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
  443. POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
  444. while (tmp < 0x3f) {
  445. if (!(readl(&power_regs->hw_power_sts) &
  446. POWER_STS_DCDC_4P2_BO)) {
  447. tmp = readl(&power_regs->hw_power_5vctrl);
  448. tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
  449. early_delay(100);
  450. writel(tmp, &power_regs->hw_power_5vctrl);
  451. break;
  452. } else {
  453. tmp++;
  454. tmp2 = readl(&power_regs->hw_power_5vctrl);
  455. tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
  456. tmp2 |= tmp <<
  457. POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
  458. writel(tmp2, &power_regs->hw_power_5vctrl);
  459. early_delay(100);
  460. }
  461. }
  462. }
  463. clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
  464. writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  465. }
  466. /**
  467. * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
  468. *
  469. * This function configures the DC-DC converter to be supplied from the 4P2
  470. * linear regulator.
  471. */
  472. static void mxs_power_init_dcdc_4p2_source(void)
  473. {
  474. struct mxs_power_regs *power_regs =
  475. (struct mxs_power_regs *)MXS_POWER_BASE;
  476. debug("SPL: Switching DC-DC converters to 4P2\n");
  477. if (!(readl(&power_regs->hw_power_dcdc4p2) &
  478. POWER_DCDC4P2_ENABLE_DCDC)) {
  479. debug("SPL: Already switched - aborting\n");
  480. hang();
  481. }
  482. mxs_enable_4p2_dcdc_input(1);
  483. if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
  484. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  485. POWER_DCDC4P2_ENABLE_DCDC);
  486. writel(POWER_5VCTRL_ENABLE_DCDC,
  487. &power_regs->hw_power_5vctrl_clr);
  488. writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
  489. &power_regs->hw_power_5vctrl_set);
  490. }
  491. }
  492. /**
  493. * mxs_power_enable_4p2() - Power up the 4P2 regulator
  494. *
  495. * This function drives the process of powering up the 4P2 linear regulator
  496. * and switching the DC-DC converter input over to the 4P2 linear regulator.
  497. */
  498. static void mxs_power_enable_4p2(void)
  499. {
  500. struct mxs_power_regs *power_regs =
  501. (struct mxs_power_regs *)MXS_POWER_BASE;
  502. uint32_t vdddctrl, vddactrl, vddioctrl;
  503. uint32_t tmp;
  504. debug("SPL: Powering up 4P2 regulator\n");
  505. vdddctrl = readl(&power_regs->hw_power_vdddctrl);
  506. vddactrl = readl(&power_regs->hw_power_vddactrl);
  507. vddioctrl = readl(&power_regs->hw_power_vddioctrl);
  508. setbits_le32(&power_regs->hw_power_vdddctrl,
  509. POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
  510. POWER_VDDDCTRL_PWDN_BRNOUT);
  511. setbits_le32(&power_regs->hw_power_vddactrl,
  512. POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
  513. POWER_VDDACTRL_PWDN_BRNOUT);
  514. setbits_le32(&power_regs->hw_power_vddioctrl,
  515. POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
  516. mxs_power_init_4p2_params();
  517. mxs_power_init_4p2_regulator();
  518. /* Shutdown battery (none present) */
  519. if (!mxs_is_batt_ready()) {
  520. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  521. POWER_DCDC4P2_BO_MASK);
  522. writel(POWER_CTRL_DCDC4P2_BO_IRQ,
  523. &power_regs->hw_power_ctrl_clr);
  524. writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
  525. &power_regs->hw_power_ctrl_clr);
  526. }
  527. mxs_power_init_dcdc_4p2_source();
  528. writel(vdddctrl, &power_regs->hw_power_vdddctrl);
  529. early_delay(20);
  530. writel(vddactrl, &power_regs->hw_power_vddactrl);
  531. early_delay(20);
  532. writel(vddioctrl, &power_regs->hw_power_vddioctrl);
  533. /*
  534. * Check if FET is enabled on either powerout and if so,
  535. * disable load.
  536. */
  537. tmp = 0;
  538. tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
  539. POWER_VDDDCTRL_DISABLE_FET);
  540. tmp |= !(readl(&power_regs->hw_power_vddactrl) &
  541. POWER_VDDACTRL_DISABLE_FET);
  542. tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
  543. POWER_VDDIOCTRL_DISABLE_FET);
  544. if (tmp)
  545. writel(POWER_CHARGE_ENABLE_LOAD,
  546. &power_regs->hw_power_charge_clr);
  547. debug("SPL: 4P2 regulator powered-up\n");
  548. }
  549. /**
  550. * mxs_boot_valid_5v() - Boot from 5V supply
  551. *
  552. * This function configures the power block to boot from valid 5V input.
  553. * This is called only if the 5V is reliable and can properly supply the
  554. * CPU. This function proceeds to configure the 4P2 converter to be supplied
  555. * from the 5V input.
  556. */
  557. static void mxs_boot_valid_5v(void)
  558. {
  559. struct mxs_power_regs *power_regs =
  560. (struct mxs_power_regs *)MXS_POWER_BASE;
  561. debug("SPL: Booting from 5V supply\n");
  562. /*
  563. * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
  564. * disconnect event. FIXME
  565. */
  566. writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
  567. &power_regs->hw_power_5vctrl_set);
  568. /* Configure polarity to check for 5V disconnection. */
  569. writel(POWER_CTRL_POLARITY_VBUSVALID |
  570. POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
  571. &power_regs->hw_power_ctrl_clr);
  572. writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
  573. &power_regs->hw_power_ctrl_clr);
  574. mxs_power_enable_4p2();
  575. }
  576. /**
  577. * mxs_powerdown() - Shut down the system
  578. *
  579. * This function powers down the CPU completely.
  580. */
  581. static void mxs_powerdown(void)
  582. {
  583. struct mxs_power_regs *power_regs =
  584. (struct mxs_power_regs *)MXS_POWER_BASE;
  585. debug("Powering Down\n");
  586. writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
  587. writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
  588. &power_regs->hw_power_reset);
  589. }
  590. /**
  591. * mxs_batt_boot() - Configure the power block to boot from battery input
  592. *
  593. * This function configures the power block to boot from the battery voltage
  594. * supply.
  595. */
  596. static void mxs_batt_boot(void)
  597. {
  598. struct mxs_power_regs *power_regs =
  599. (struct mxs_power_regs *)MXS_POWER_BASE;
  600. debug("SPL: Configuring power block to boot from battery\n");
  601. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
  602. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
  603. clrbits_le32(&power_regs->hw_power_dcdc4p2,
  604. POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
  605. writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
  606. /* 5V to battery handoff. */
  607. setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  608. early_delay(30);
  609. clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
  610. writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
  611. clrsetbits_le32(&power_regs->hw_power_minpwr,
  612. POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
  613. mxs_power_set_linreg();
  614. clrbits_le32(&power_regs->hw_power_vdddctrl,
  615. POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
  616. clrbits_le32(&power_regs->hw_power_vddactrl,
  617. POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
  618. clrbits_le32(&power_regs->hw_power_vddioctrl,
  619. POWER_VDDIOCTRL_DISABLE_FET);
  620. setbits_le32(&power_regs->hw_power_5vctrl,
  621. POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
  622. setbits_le32(&power_regs->hw_power_5vctrl,
  623. POWER_5VCTRL_ENABLE_DCDC);
  624. clrsetbits_le32(&power_regs->hw_power_5vctrl,
  625. POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
  626. 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
  627. mxs_power_enable_4p2();
  628. }
  629. /**
  630. * mxs_handle_5v_conflict() - Test if the 5V input is reliable
  631. *
  632. * This function tests if the 5V input can reliably supply the system. If it
  633. * can, then proceed to configuring the system to boot from 5V source, otherwise
  634. * try booting from battery supply. If we can not boot from battery supply
  635. * either, shut down the system.
  636. */
  637. static void mxs_handle_5v_conflict(void)
  638. {
  639. struct mxs_power_regs *power_regs =
  640. (struct mxs_power_regs *)MXS_POWER_BASE;
  641. uint32_t tmp;
  642. debug("SPL: Resolving 5V conflict\n");
  643. setbits_le32(&power_regs->hw_power_vddioctrl,
  644. POWER_VDDIOCTRL_BO_OFFSET_MASK);
  645. for (;;) {
  646. tmp = readl(&power_regs->hw_power_sts);
  647. if (tmp & POWER_STS_VDDIO_BO) {
  648. /*
  649. * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
  650. * unreliable
  651. */
  652. debug("SPL: VDDIO has a brownout\n");
  653. mxs_powerdown();
  654. break;
  655. }
  656. if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
  657. debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
  658. mxs_boot_valid_5v();
  659. break;
  660. } else {
  661. debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
  662. mxs_powerdown();
  663. break;
  664. }
  665. /*
  666. * TODO: I can't see this being reached. We'll either
  667. * powerdown or boot from a stable 5V supply.
  668. */
  669. if (tmp & POWER_STS_PSWITCH_MASK) {
  670. debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
  671. mxs_batt_boot();
  672. break;
  673. }
  674. }
  675. }
  676. /**
  677. * mxs_5v_boot() - Configure the power block to boot from 5V input
  678. *
  679. * This function handles configuration of the power block when supplied by
  680. * a 5V input.
  681. */
  682. static void mxs_5v_boot(void)
  683. {
  684. struct mxs_power_regs *power_regs =
  685. (struct mxs_power_regs *)MXS_POWER_BASE;
  686. debug("SPL: Configuring power block to boot from 5V input\n");
  687. /*
  688. * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
  689. * but their implementation always returns 1 so we omit it here.
  690. */
  691. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  692. debug("SPL: 5V VDD good\n");
  693. mxs_boot_valid_5v();
  694. return;
  695. }
  696. early_delay(1000);
  697. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  698. debug("SPL: 5V VDD good (after delay)\n");
  699. mxs_boot_valid_5v();
  700. return;
  701. }
  702. debug("SPL: 5V VDD not good\n");
  703. mxs_handle_5v_conflict();
  704. }
  705. /**
  706. * mxs_init_batt_bo() - Configure battery brownout threshold
  707. *
  708. * This function configures the battery input brownout threshold. The value
  709. * at which the battery brownout happens is configured to 3.0V in the code.
  710. */
  711. static void mxs_init_batt_bo(void)
  712. {
  713. struct mxs_power_regs *power_regs =
  714. (struct mxs_power_regs *)MXS_POWER_BASE;
  715. debug("SPL: Initialising battery brown-out level to 3.0V\n");
  716. /* Brownout at 3V */
  717. clrsetbits_le32(&power_regs->hw_power_battmonitor,
  718. POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
  719. 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
  720. writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  721. writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
  722. }
  723. /**
  724. * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
  725. *
  726. * This function turns off the VDDD linear regulator and therefore makes
  727. * the VDDD rail be supplied only by the DC-DC converter.
  728. */
  729. static void mxs_switch_vddd_to_dcdc_source(void)
  730. {
  731. struct mxs_power_regs *power_regs =
  732. (struct mxs_power_regs *)MXS_POWER_BASE;
  733. debug("SPL: Switching VDDD to DC-DC converters\n");
  734. clrsetbits_le32(&power_regs->hw_power_vdddctrl,
  735. POWER_VDDDCTRL_LINREG_OFFSET_MASK,
  736. POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
  737. clrbits_le32(&power_regs->hw_power_vdddctrl,
  738. POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
  739. POWER_VDDDCTRL_DISABLE_STEPPING);
  740. }
  741. /**
  742. * mxs_power_configure_power_source() - Configure power block source
  743. *
  744. * This function is the core of the power configuration logic. The function
  745. * selects the power block input source and configures the whole power block
  746. * accordingly. After the configuration is complete and the system is stable
  747. * again, the function switches the CPU clock source back to PLL. Finally,
  748. * the function switches the voltage rails to DC-DC converter.
  749. */
  750. static void mxs_power_configure_power_source(void)
  751. {
  752. int batt_ready, batt_good;
  753. struct mxs_power_regs *power_regs =
  754. (struct mxs_power_regs *)MXS_POWER_BASE;
  755. struct mxs_lradc_regs *lradc_regs =
  756. (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  757. debug("SPL: Configuring power source\n");
  758. mxs_power_setup_dcdc_clocksource();
  759. mxs_src_power_init();
  760. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  761. batt_ready = mxs_is_batt_ready();
  762. if (batt_ready) {
  763. /* 5V source detected, good battery detected. */
  764. mxs_batt_boot();
  765. } else {
  766. batt_good = mxs_is_batt_good();
  767. if (!batt_good) {
  768. /* 5V source detected, bad battery detected. */
  769. writel(LRADC_CONVERSION_AUTOMATIC,
  770. &lradc_regs->hw_lradc_conversion_clr);
  771. clrbits_le32(&power_regs->hw_power_battmonitor,
  772. POWER_BATTMONITOR_BATT_VAL_MASK);
  773. }
  774. mxs_5v_boot();
  775. }
  776. } else {
  777. /* 5V not detected, booting from battery. */
  778. mxs_batt_boot();
  779. }
  780. /*
  781. * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
  782. * from USB VBUS
  783. */
  784. mxs_power_clock2pll();
  785. mxs_init_batt_bo();
  786. mxs_switch_vddd_to_dcdc_source();
  787. #ifdef CONFIG_MX23
  788. /* Fire up the VDDMEM LinReg now that we're all set. */
  789. debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
  790. writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
  791. &power_regs->hw_power_vddmemctrl);
  792. #endif
  793. }
  794. /**
  795. * mxs_enable_output_rail_protection() - Enable power rail protection
  796. *
  797. * This function enables overload protection on the power rails. This is
  798. * triggered if the power rails' voltage drops rapidly due to overload and
  799. * in such case, the supply to the powerrail is cut-off, protecting the
  800. * CPU from damage. Note that under such condition, the system will likely
  801. * crash or misbehave.
  802. */
  803. static void mxs_enable_output_rail_protection(void)
  804. {
  805. struct mxs_power_regs *power_regs =
  806. (struct mxs_power_regs *)MXS_POWER_BASE;
  807. debug("SPL: Enabling output rail protection\n");
  808. writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
  809. POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  810. setbits_le32(&power_regs->hw_power_vdddctrl,
  811. POWER_VDDDCTRL_PWDN_BRNOUT);
  812. setbits_le32(&power_regs->hw_power_vddactrl,
  813. POWER_VDDACTRL_PWDN_BRNOUT);
  814. setbits_le32(&power_regs->hw_power_vddioctrl,
  815. POWER_VDDIOCTRL_PWDN_BRNOUT);
  816. }
  817. /**
  818. * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
  819. *
  820. * This function tests if the VDDIO rail is supplied by linear regulator
  821. * or by the DC-DC converter. Returns 1 if powered by linear regulator,
  822. * returns 0 if powered by the DC-DC converter.
  823. */
  824. static int mxs_get_vddio_power_source_off(void)
  825. {
  826. struct mxs_power_regs *power_regs =
  827. (struct mxs_power_regs *)MXS_POWER_BASE;
  828. uint32_t tmp;
  829. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  830. tmp = readl(&power_regs->hw_power_vddioctrl);
  831. if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
  832. if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
  833. POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
  834. return 1;
  835. }
  836. }
  837. if (!(readl(&power_regs->hw_power_5vctrl) &
  838. POWER_5VCTRL_ENABLE_DCDC)) {
  839. if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
  840. POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
  841. return 1;
  842. }
  843. }
  844. }
  845. return 0;
  846. }
  847. /**
  848. * mxs_get_vddd_power_source_off() - Get VDDD rail power source
  849. *
  850. * This function tests if the VDDD rail is supplied by linear regulator
  851. * or by the DC-DC converter. Returns 1 if powered by linear regulator,
  852. * returns 0 if powered by the DC-DC converter.
  853. */
  854. static int mxs_get_vddd_power_source_off(void)
  855. {
  856. struct mxs_power_regs *power_regs =
  857. (struct mxs_power_regs *)MXS_POWER_BASE;
  858. uint32_t tmp;
  859. tmp = readl(&power_regs->hw_power_vdddctrl);
  860. if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
  861. if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
  862. POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
  863. return 1;
  864. }
  865. }
  866. if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
  867. if (!(readl(&power_regs->hw_power_5vctrl) &
  868. POWER_5VCTRL_ENABLE_DCDC)) {
  869. return 1;
  870. }
  871. }
  872. if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
  873. if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
  874. POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
  875. return 1;
  876. }
  877. }
  878. return 0;
  879. }
  880. struct mxs_vddx_cfg {
  881. uint32_t *reg;
  882. uint8_t step_mV;
  883. uint16_t lowest_mV;
  884. int (*powered_by_linreg)(void);
  885. uint32_t trg_mask;
  886. uint32_t bo_irq;
  887. uint32_t bo_enirq;
  888. uint32_t bo_offset_mask;
  889. uint32_t bo_offset_offset;
  890. };
  891. static const struct mxs_vddx_cfg mxs_vddio_cfg = {
  892. .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
  893. hw_power_vddioctrl),
  894. #if defined(CONFIG_MX23)
  895. .step_mV = 25,
  896. #else
  897. .step_mV = 50,
  898. #endif
  899. .lowest_mV = 2800,
  900. .powered_by_linreg = mxs_get_vddio_power_source_off,
  901. .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
  902. .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
  903. .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
  904. .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
  905. .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
  906. };
  907. static const struct mxs_vddx_cfg mxs_vddd_cfg = {
  908. .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
  909. hw_power_vdddctrl),
  910. .step_mV = 25,
  911. .lowest_mV = 800,
  912. .powered_by_linreg = mxs_get_vddd_power_source_off,
  913. .trg_mask = POWER_VDDDCTRL_TRG_MASK,
  914. .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
  915. .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
  916. .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
  917. .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
  918. };
  919. #ifdef CONFIG_MX23
  920. static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
  921. .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
  922. hw_power_vddmemctrl),
  923. .step_mV = 50,
  924. .lowest_mV = 1700,
  925. .powered_by_linreg = NULL,
  926. .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
  927. .bo_irq = 0,
  928. .bo_enirq = 0,
  929. .bo_offset_mask = 0,
  930. .bo_offset_offset = 0,
  931. };
  932. #endif
  933. /**
  934. * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
  935. * @cfg: Configuration data of the DC-DC converter rail
  936. * @new_target: New target voltage of the DC-DC converter rail
  937. * @new_brownout: New brownout trigger voltage
  938. *
  939. * This function configures the output voltage on the DC-DC converter rail.
  940. * The rail is selected by the @cfg argument. The new voltage target is
  941. * selected by the @new_target and the voltage is specified in mV. The
  942. * new brownout value is selected by the @new_brownout argument and the
  943. * value is also in mV.
  944. */
  945. static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
  946. uint32_t new_target, uint32_t new_brownout)
  947. {
  948. struct mxs_power_regs *power_regs =
  949. (struct mxs_power_regs *)MXS_POWER_BASE;
  950. uint32_t cur_target, diff, bo_int = 0;
  951. uint32_t powered_by_linreg = 0;
  952. int adjust_up, tmp;
  953. new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
  954. cfg->step_mV);
  955. cur_target = readl(cfg->reg);
  956. cur_target &= cfg->trg_mask;
  957. cur_target *= cfg->step_mV;
  958. cur_target += cfg->lowest_mV;
  959. adjust_up = new_target > cur_target;
  960. if (cfg->powered_by_linreg)
  961. powered_by_linreg = cfg->powered_by_linreg();
  962. if (adjust_up && cfg->bo_irq) {
  963. if (powered_by_linreg) {
  964. bo_int = readl(cfg->reg);
  965. clrbits_le32(cfg->reg, cfg->bo_enirq);
  966. }
  967. setbits_le32(cfg->reg, cfg->bo_offset_mask);
  968. }
  969. do {
  970. if (abs(new_target - cur_target) > 100) {
  971. if (adjust_up)
  972. diff = cur_target + 100;
  973. else
  974. diff = cur_target - 100;
  975. } else {
  976. diff = new_target;
  977. }
  978. diff -= cfg->lowest_mV;
  979. diff /= cfg->step_mV;
  980. clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
  981. if (powered_by_linreg ||
  982. (readl(&power_regs->hw_power_sts) &
  983. POWER_STS_VDD5V_GT_VDDIO))
  984. early_delay(500);
  985. else {
  986. for (;;) {
  987. tmp = readl(&power_regs->hw_power_sts);
  988. if (tmp & POWER_STS_DC_OK)
  989. break;
  990. }
  991. }
  992. cur_target = readl(cfg->reg);
  993. cur_target &= cfg->trg_mask;
  994. cur_target *= cfg->step_mV;
  995. cur_target += cfg->lowest_mV;
  996. } while (new_target > cur_target);
  997. if (cfg->bo_irq) {
  998. if (adjust_up && powered_by_linreg) {
  999. writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
  1000. if (bo_int & cfg->bo_enirq)
  1001. setbits_le32(cfg->reg, cfg->bo_enirq);
  1002. }
  1003. clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
  1004. new_brownout << cfg->bo_offset_offset);
  1005. }
  1006. }
  1007. /**
  1008. * mxs_setup_batt_detect() - Start the battery voltage measurement logic
  1009. *
  1010. * This function starts and configures the LRADC block. This allows the
  1011. * power initialization code to measure battery voltage and based on this
  1012. * knowledge, decide whether to boot at all, boot from battery or boot
  1013. * from 5V input.
  1014. */
  1015. static void mxs_setup_batt_detect(void)
  1016. {
  1017. debug("SPL: Starting battery voltage measurement logic\n");
  1018. mxs_lradc_init();
  1019. mxs_lradc_enable_batt_measurement();
  1020. early_delay(10);
  1021. }
  1022. /**
  1023. * mxs_ungate_power() - Ungate the POWER block
  1024. *
  1025. * This function ungates clock to the power block. In case the power block
  1026. * was still gated at this point, it will not be possible to configure the
  1027. * block and therefore the power initialization would fail. This function
  1028. * is only needed on i.MX233, on i.MX28 the power block is always ungated.
  1029. */
  1030. static void mxs_ungate_power(void)
  1031. {
  1032. #ifdef CONFIG_MX23
  1033. struct mxs_power_regs *power_regs =
  1034. (struct mxs_power_regs *)MXS_POWER_BASE;
  1035. writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
  1036. #endif
  1037. }
  1038. /**
  1039. * mxs_power_init() - The power block init main function
  1040. *
  1041. * This function calls all the power block initialization functions in
  1042. * proper sequence to start the power block.
  1043. */
  1044. void mxs_power_init(void)
  1045. {
  1046. struct mxs_power_regs *power_regs =
  1047. (struct mxs_power_regs *)MXS_POWER_BASE;
  1048. debug("SPL: Initialising Power Block\n");
  1049. mxs_ungate_power();
  1050. mxs_power_clock2xtal();
  1051. mxs_power_set_auto_restart();
  1052. mxs_power_set_linreg();
  1053. mxs_power_setup_5v_detect();
  1054. mxs_setup_batt_detect();
  1055. mxs_power_configure_power_source();
  1056. mxs_enable_output_rail_protection();
  1057. debug("SPL: Setting VDDIO to 3V3 (brownout @ 3v15)\n");
  1058. mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
  1059. debug("SPL: Setting VDDD to 1V55 (brownout @ 1v400)\n");
  1060. mxs_power_set_vddx(&mxs_vddd_cfg, 1550, 1400);
  1061. #ifdef CONFIG_MX23
  1062. debug("SPL: Setting mx23 VDDMEM to 2V5 (brownout @ 1v7)\n");
  1063. mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
  1064. #endif
  1065. writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
  1066. POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
  1067. POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
  1068. POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
  1069. writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
  1070. early_delay(1000);
  1071. }
  1072. #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
  1073. /**
  1074. * mxs_power_wait_pswitch() - Wait for power switch to be pressed
  1075. *
  1076. * This function waits until the power-switch was pressed to start booting
  1077. * the board.
  1078. */
  1079. void mxs_power_wait_pswitch(void)
  1080. {
  1081. struct mxs_power_regs *power_regs =
  1082. (struct mxs_power_regs *)MXS_POWER_BASE;
  1083. debug("SPL: Waiting for power switch input\n");
  1084. while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
  1085. ;
  1086. }
  1087. #endif