mxs.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 common code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <hang.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/mach-imx/dma.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/iomux.h>
  20. #include <asm/arch/imx-regs.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <linux/compiler.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
  25. __weak void lowlevel_init(void) {}
  26. void reset_cpu(ulong ignored) __attribute__((noreturn));
  27. void reset_cpu(ulong ignored)
  28. {
  29. struct mxs_rtc_regs *rtc_regs =
  30. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  31. struct mxs_lcdif_regs *lcdif_regs =
  32. (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  33. /*
  34. * Shut down the LCD controller as it interferes with BootROM boot mode
  35. * pads sampling.
  36. */
  37. writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
  38. /* Wait 1 uS before doing the actual watchdog reset */
  39. writel(1, &rtc_regs->hw_rtc_watchdog);
  40. writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
  41. /* Endless loop, reset will exit from here */
  42. for (;;)
  43. ;
  44. }
  45. /*
  46. * This function will craft a jumptable at 0x0 which will redirect interrupt
  47. * vectoring to proper location of U-Boot in RAM.
  48. *
  49. * The structure of the jumptable will be as follows:
  50. * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
  51. * <destination address> ... for each previous ldr, thus also repeated 8 times
  52. *
  53. * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
  54. * offset 0x18 from current value of PC register. Note that PC is already
  55. * incremented by 4 when computing the offset, so the effective offset is
  56. * actually 0x20, this the associated <destination address>. Loading the PC
  57. * register with an address performs a jump to that address.
  58. */
  59. void mx28_fixup_vt(uint32_t start_addr)
  60. {
  61. /* ldr pc, [pc, #0x18] */
  62. const uint32_t ldr_pc = 0xe59ff018;
  63. /* Jumptable location is 0x0 */
  64. uint32_t *vt = (uint32_t *)0x0;
  65. int i;
  66. for (i = 0; i < 8; i++) {
  67. /* cppcheck-suppress nullPointer */
  68. vt[i] = ldr_pc;
  69. /* cppcheck-suppress nullPointer */
  70. vt[i + 8] = start_addr + (4 * i);
  71. }
  72. }
  73. #ifdef CONFIG_ARCH_MISC_INIT
  74. int arch_misc_init(void)
  75. {
  76. mx28_fixup_vt(gd->relocaddr);
  77. return 0;
  78. }
  79. #endif
  80. int arch_cpu_init(void)
  81. {
  82. struct mxs_clkctrl_regs *clkctrl_regs =
  83. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  84. extern uint32_t _start;
  85. mx28_fixup_vt((uint32_t)&_start);
  86. /*
  87. * Enable NAND clock
  88. */
  89. /* Set bypass bit */
  90. writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
  91. &clkctrl_regs->hw_clkctrl_clkseq_set);
  92. /* Set GPMI clock to ref_xtal / 1 */
  93. clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
  94. while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
  95. ;
  96. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
  97. CLKCTRL_GPMI_DIV_MASK, 1);
  98. udelay(1000);
  99. /*
  100. * Configure GPIO unit
  101. */
  102. mxs_gpio_init();
  103. #ifdef CONFIG_APBH_DMA
  104. /* Start APBH DMA */
  105. mxs_dma_init();
  106. #endif
  107. return 0;
  108. }
  109. u32 get_cpu_rev(void)
  110. {
  111. struct mxs_digctl_regs *digctl_regs =
  112. (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
  113. uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
  114. switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
  115. case HW_DIGCTL_CHIPID_MX23:
  116. switch (rev) {
  117. case 0x0:
  118. case 0x1:
  119. case 0x2:
  120. case 0x3:
  121. case 0x4:
  122. return (MXC_CPU_MX23 << 12) | (rev + 0x10);
  123. default:
  124. return 0;
  125. }
  126. case HW_DIGCTL_CHIPID_MX28:
  127. switch (rev) {
  128. case 0x1:
  129. return (MXC_CPU_MX28 << 12) | 0x12;
  130. default:
  131. return 0;
  132. }
  133. default:
  134. return 0;
  135. }
  136. }
  137. #if defined(CONFIG_DISPLAY_CPUINFO)
  138. const char *get_imx_type(u32 imxtype)
  139. {
  140. switch (imxtype) {
  141. case MXC_CPU_MX23:
  142. return "23";
  143. case MXC_CPU_MX28:
  144. return "28";
  145. default:
  146. return "??";
  147. }
  148. }
  149. int print_cpuinfo(void)
  150. {
  151. u32 cpurev;
  152. struct mxs_spl_data *data = MXS_SPL_DATA;
  153. cpurev = get_cpu_rev();
  154. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  155. get_imx_type((cpurev & 0xFF000) >> 12),
  156. (cpurev & 0x000F0) >> 4,
  157. (cpurev & 0x0000F) >> 0,
  158. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  159. printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
  160. return 0;
  161. }
  162. #endif
  163. int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  164. {
  165. printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  166. printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
  167. printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
  168. printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
  169. return 0;
  170. }
  171. /*
  172. * Initializes on-chip ethernet controllers.
  173. */
  174. #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
  175. int cpu_eth_init(bd_t *bis)
  176. {
  177. struct mxs_clkctrl_regs *clkctrl_regs =
  178. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  179. /* Turn on ENET clocks */
  180. clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
  181. CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
  182. /* Set up ENET PLL for 50 MHz */
  183. /* Power on ENET PLL */
  184. writel(CLKCTRL_PLL2CTRL0_POWER,
  185. &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
  186. udelay(10);
  187. /* Gate on ENET PLL */
  188. writel(CLKCTRL_PLL2CTRL0_CLKGATE,
  189. &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
  190. /* Enable pad output */
  191. setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
  192. return 0;
  193. }
  194. #endif
  195. __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
  196. {
  197. mac[0] = 0x00;
  198. mac[1] = 0x04; /* Use FSL vendor MAC address by default */
  199. if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
  200. mac[5] += 1;
  201. }
  202. #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
  203. #define MXS_OCOTP_MAX_TIMEOUT 1000000
  204. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  205. {
  206. struct mxs_ocotp_regs *ocotp_regs =
  207. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  208. uint32_t data;
  209. memset(mac, 0, 6);
  210. writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  211. if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  212. MXS_OCOTP_MAX_TIMEOUT)) {
  213. printf("MXS FEC: Can't get MAC from OCOTP\n");
  214. return;
  215. }
  216. data = readl(&ocotp_regs->hw_ocotp_cust0);
  217. mac[2] = (data >> 24) & 0xff;
  218. mac[3] = (data >> 16) & 0xff;
  219. mac[4] = (data >> 8) & 0xff;
  220. mac[5] = data & 0xff;
  221. mx28_adjust_mac(dev_id, mac);
  222. }
  223. #else
  224. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  225. {
  226. memset(mac, 0, 6);
  227. }
  228. #endif
  229. int mxs_dram_init(void)
  230. {
  231. struct mxs_spl_data *data = MXS_SPL_DATA;
  232. if (data->mem_dram_size == 0) {
  233. printf("MXS:\n"
  234. "Error, the RAM size passed up from SPL is 0!\n");
  235. hang();
  236. }
  237. gd->ram_size = data->mem_dram_size;
  238. return 0;
  239. }
  240. U_BOOT_CMD(
  241. clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
  242. "display clocks",
  243. ""
  244. );