socrates.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003, Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. */
  12. #include <common.h>
  13. #include <clock_legacy.h>
  14. #include <env.h>
  15. #include <pci.h>
  16. #include <asm/processor.h>
  17. #include <asm/immap_85xx.h>
  18. #include <ioports.h>
  19. #include <flash.h>
  20. #include <linux/libfdt.h>
  21. #include <fdt_support.h>
  22. #include <asm/io.h>
  23. #include <i2c.h>
  24. #include <mb862xx.h>
  25. #include <video_fb.h>
  26. #include "upm_table.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. extern flash_info_t flash_info[]; /* FLASH chips info */
  29. extern GraphicDevice mb862xx;
  30. void local_bus_init (void);
  31. ulong flash_get_size (ulong base, int banknum);
  32. int checkboard (void)
  33. {
  34. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35. char buf[64];
  36. int f;
  37. int i = env_get_f("serial#", buf, sizeof(buf));
  38. #ifdef CONFIG_PCI
  39. char *src;
  40. #endif
  41. puts("Board: Socrates");
  42. if (i > 0) {
  43. puts(", serial# ");
  44. puts(buf);
  45. }
  46. putc('\n');
  47. #if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
  48. /* Check the PCI_clk sel bit */
  49. if (in_be32(&gur->porpllsr) & (1<<15)) {
  50. src = "SYSCLK";
  51. f = CONFIG_SYS_CLK_FREQ;
  52. } else {
  53. src = "PCI_CLK";
  54. f = CONFIG_PCI_CLK_FREQ;
  55. }
  56. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  57. #else
  58. printf ("PCI1: disabled\n");
  59. #endif
  60. /*
  61. * Initialize local bus.
  62. */
  63. local_bus_init ();
  64. return 0;
  65. }
  66. int misc_init_r (void)
  67. {
  68. /*
  69. * Adjust flash start and offset to detected values
  70. */
  71. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  72. gd->bd->bi_flashoffset = 0;
  73. /*
  74. * Check if boot FLASH isn't max size
  75. */
  76. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  77. set_lbc_or(0, gd->bd->bi_flashstart |
  78. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  79. set_lbc_br(0, gd->bd->bi_flashstart |
  80. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  81. /*
  82. * Re-check to get correct base address
  83. */
  84. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  85. }
  86. /*
  87. * Check if only one FLASH bank is available
  88. */
  89. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  90. set_lbc_or(1, 0);
  91. set_lbc_br(1, 0);
  92. /*
  93. * Re-do flash protection upon new addresses
  94. */
  95. flash_protect (FLAG_PROTECT_CLEAR,
  96. gd->bd->bi_flashstart, 0xffffffff,
  97. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  98. /* Monitor protection ON by default */
  99. flash_protect (FLAG_PROTECT_SET,
  100. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
  101. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  102. /* Environment protection ON by default */
  103. flash_protect (FLAG_PROTECT_SET,
  104. CONFIG_ENV_ADDR,
  105. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  106. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  107. /* Redundant environment protection ON by default */
  108. flash_protect (FLAG_PROTECT_SET,
  109. CONFIG_ENV_ADDR_REDUND,
  110. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  111. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  112. }
  113. #if defined(CONFIG_DM_PCI)
  114. pci_init();
  115. #endif
  116. return 0;
  117. }
  118. /*
  119. * Initialize Local Bus
  120. */
  121. void local_bus_init (void)
  122. {
  123. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  124. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  125. sys_info_t sysinfo;
  126. uint clkdiv;
  127. uint lbc_mhz;
  128. uint lcrr = CONFIG_SYS_LBC_LCRR;
  129. get_sys_info (&sysinfo);
  130. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  131. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  132. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  133. if (lbc_mhz >= 66)
  134. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  135. else
  136. lcrr |= LCRR_DBYP; /* DLL Bypass */
  137. out_be32 (&lbc->lcrr, lcrr);
  138. asm ("sync;isync;msync");
  139. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  140. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  141. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  142. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  143. /* Init UPMA for FPGA access */
  144. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  145. upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
  146. /* Init UPMB for Lime controller access */
  147. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  148. upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
  149. }
  150. #ifdef CONFIG_BOARD_EARLY_INIT_R
  151. int board_early_init_r (void)
  152. {
  153. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  154. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  155. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  156. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  157. udelay(200);
  158. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  159. return (0);
  160. }
  161. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  162. #ifdef CONFIG_OF_BOARD_SETUP
  163. int ft_board_setup(void *blob, bd_t *bd)
  164. {
  165. u32 val[12];
  166. int rc, i = 0;
  167. ft_cpu_setup(blob, bd);
  168. /* Fixup NOR FLASH mapping */
  169. val[i++] = 0; /* chip select number */
  170. val[i++] = 0; /* always 0 */
  171. val[i++] = gd->bd->bi_flashstart;
  172. val[i++] = gd->bd->bi_flashsize;
  173. #if defined(CONFIG_VIDEO_MB862xx)
  174. if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
  175. /* Fixup LIME mapping */
  176. val[i++] = 2; /* chip select number */
  177. val[i++] = 0; /* always 0 */
  178. val[i++] = CONFIG_SYS_LIME_BASE;
  179. val[i++] = CONFIG_SYS_LIME_SIZE;
  180. }
  181. #endif
  182. /* Fixup FPGA mapping */
  183. val[i++] = 3; /* chip select number */
  184. val[i++] = 0; /* always 0 */
  185. val[i++] = CONFIG_SYS_FPGA_BASE;
  186. val[i++] = CONFIG_SYS_FPGA_SIZE;
  187. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  188. val, i * sizeof(u32), 1);
  189. if (rc)
  190. printf("Unable to update localbus ranges, err=%s\n",
  191. fdt_strerror(rc));
  192. return 0;
  193. }
  194. #endif /* CONFIG_OF_BOARD_SETUP */
  195. #if defined(CONFIG_OF_SEPARATE)
  196. void *board_fdt_blob_setup(void)
  197. {
  198. void *fw_dtb;
  199. fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
  200. if (fdt_magic(fw_dtb) != FDT_MAGIC) {
  201. printf("DTB is not passed via %x\n", (u32)fw_dtb);
  202. return NULL;
  203. }
  204. return fw_dtb;
  205. }
  206. #endif
  207. int get_serial_clock(void)
  208. {
  209. return 333333330;
  210. }