spl.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2013 Freescale Semiconductor, Inc.
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <console.h>
  7. #include <env_internal.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <ns16550.h>
  11. #include <nand.h>
  12. #include <i2c.h>
  13. #include <mmc.h>
  14. #include <fsl_esdhc.h>
  15. #include <spi_flash.h>
  16. #include "../common/sleep.h"
  17. #include "../common/spl.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. phys_size_t get_effective_memsize(void)
  20. {
  21. return CONFIG_SYS_L3_SIZE;
  22. }
  23. unsigned long get_board_sys_clk(void)
  24. {
  25. return CONFIG_SYS_CLK_FREQ;
  26. }
  27. unsigned long get_board_ddr_clk(void)
  28. {
  29. return CONFIG_DDR_CLK_FREQ;
  30. }
  31. #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
  32. void board_init_f(ulong bootflag)
  33. {
  34. u32 plat_ratio, sys_clk, uart_clk;
  35. #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  36. u32 porsr1, pinctl;
  37. u32 svr = get_svr();
  38. #endif
  39. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  40. #if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
  41. if (IS_SVR_REV(svr, 1, 0)) {
  42. /*
  43. * There is T1040 SoC issue where NOR, FPGA are inaccessible
  44. * during NAND boot because IFC signals > IFC_AD7 are not
  45. * enabled. This workaround changes RCW source to make all
  46. * signals enabled.
  47. */
  48. porsr1 = in_be32(&gur->porsr1);
  49. pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
  50. | 0x24800000);
  51. out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
  52. pinctl);
  53. }
  54. #endif
  55. /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  56. memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  57. /* Update GD pointer */
  58. gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  59. #ifdef CONFIG_DEEP_SLEEP
  60. /* disable the console if boot from deep sleep */
  61. if (is_warm_boot())
  62. fsl_dp_disable_console();
  63. #endif
  64. /* compiler optimization barrier needed for GCC >= 3.4 */
  65. __asm__ __volatile__("" : : : "memory");
  66. console_init_f();
  67. /* initialize selected port with appropriate baud rate */
  68. sys_clk = get_board_sys_clk();
  69. plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  70. uart_clk = sys_clk * plat_ratio / 2;
  71. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  72. uart_clk / 16 / CONFIG_BAUDRATE);
  73. relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  74. }
  75. void board_init_r(gd_t *gd, ulong dest_addr)
  76. {
  77. bd_t *bd;
  78. bd = (bd_t *)(gd + sizeof(gd_t));
  79. memset(bd, 0, sizeof(bd_t));
  80. gd->bd = bd;
  81. bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  82. bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  83. arch_cpu_init();
  84. get_clocks();
  85. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  86. CONFIG_SPL_RELOC_MALLOC_SIZE);
  87. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  88. #ifdef CONFIG_SPL_MMC_BOOT
  89. mmc_initialize(bd);
  90. #endif
  91. /* relocate environment function pointers etc. */
  92. #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
  93. defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  94. #ifdef CONFIG_SPL_NAND_BOOT
  95. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  96. (uchar *)SPL_ENV_ADDR);
  97. #endif
  98. #ifdef CONFIG_SPL_MMC_BOOT
  99. mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  100. (uchar *)SPL_ENV_ADDR);
  101. #endif
  102. #ifdef CONFIG_SPL_SPI_BOOT
  103. fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  104. (uchar *)SPL_ENV_ADDR);
  105. #endif
  106. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  107. gd->env_valid = ENV_VALID;
  108. #endif
  109. i2c_init_all();
  110. puts("\n\n");
  111. dram_init();
  112. #ifdef CONFIG_SPL_MMC_BOOT
  113. mmc_boot();
  114. #elif defined(CONFIG_SPL_SPI_BOOT)
  115. fsl_spi_boot();
  116. #elif defined(CONFIG_SPL_NAND_BOOT)
  117. nand_boot();
  118. #endif
  119. }