diu.c 2.6 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <command.h>
  9. #include <linux/ctype.h>
  10. #include <asm/io.h>
  11. #include <stdio_dev.h>
  12. #include <video_fb.h>
  13. #include <fsl_diu_fb.h>
  14. #include "../common/qixis.h"
  15. #include "../common/diu_ch7301.h"
  16. #include "t1040qds.h"
  17. #include "t1040qds_qixis.h"
  18. /*
  19. * DIU Area Descriptor
  20. *
  21. * Note that we need to byte-swap the value before it's written to the AD
  22. * register. So even though the registers don't look like they're in the same
  23. * bit positions as they are on the MPC8610, the same value is written to the
  24. * AD register on the MPC8610 and on the P1022.
  25. */
  26. #define AD_BYTE_F 0x10000000
  27. #define AD_ALPHA_C_SHIFT 25
  28. #define AD_BLUE_C_SHIFT 23
  29. #define AD_GREEN_C_SHIFT 21
  30. #define AD_RED_C_SHIFT 19
  31. #define AD_PIXEL_S_SHIFT 16
  32. #define AD_COMP_3_SHIFT 12
  33. #define AD_COMP_2_SHIFT 8
  34. #define AD_COMP_1_SHIFT 4
  35. #define AD_COMP_0_SHIFT 0
  36. void diu_set_pixel_clock(unsigned int pixclock)
  37. {
  38. unsigned long speed_ccb, temp;
  39. u32 pixval;
  40. int ret = 0;
  41. speed_ccb = get_bus_freq(0);
  42. temp = 1000000000 / pixclock;
  43. temp *= 1000;
  44. pixval = speed_ccb / temp;
  45. /* Program HDMI encoder */
  46. /* Switch channel to DIU */
  47. select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
  48. /* Set dispaly encoder */
  49. ret = diu_set_dvi_encoder(temp);
  50. if (ret) {
  51. puts("Failed to set DVI encoder\n");
  52. return;
  53. }
  54. /* Switch channel to default */
  55. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  56. /* Program pixel clock */
  57. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
  58. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  59. /* enable clock*/
  60. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
  61. ((pixval << PXCK_BITS_START) & PXCK_MASK));
  62. }
  63. int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  64. {
  65. u32 pixel_format;
  66. u8 sw;
  67. /*Route I2C4 to DIU system as HSYNC/VSYNC*/
  68. sw = QIXIS_READ(brdcfg[5]);
  69. QIXIS_WRITE(brdcfg[5],
  70. ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
  71. /*Configure Display ouput port as HDMI*/
  72. sw = QIXIS_READ(brdcfg[15]);
  73. QIXIS_WRITE(brdcfg[15],
  74. ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
  75. | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
  76. pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  77. (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  78. (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  79. (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  80. (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  81. printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
  82. return fsl_diu_init(xres, yres, pixel_format, 0);
  83. }