spl.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2014 Freescale Semiconductor, Inc.
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <console.h>
  7. #include <env_internal.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <ns16550.h>
  11. #include <nand.h>
  12. #include <i2c.h>
  13. #include <mmc.h>
  14. #include <fsl_esdhc.h>
  15. #include <spi_flash.h>
  16. #include "../common/qixis.h"
  17. #include "t102xqds_qixis.h"
  18. #include "../common/spl.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. phys_size_t get_effective_memsize(void)
  21. {
  22. return CONFIG_SYS_L3_SIZE;
  23. }
  24. unsigned long get_board_sys_clk(void)
  25. {
  26. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  27. switch (sysclk_conf & 0x0F) {
  28. case QIXIS_SYSCLK_83:
  29. return 83333333;
  30. case QIXIS_SYSCLK_100:
  31. return 100000000;
  32. case QIXIS_SYSCLK_125:
  33. return 125000000;
  34. case QIXIS_SYSCLK_133:
  35. return 133333333;
  36. case QIXIS_SYSCLK_150:
  37. return 150000000;
  38. case QIXIS_SYSCLK_160:
  39. return 160000000;
  40. case QIXIS_SYSCLK_166:
  41. return 166666666;
  42. }
  43. return 66666666;
  44. }
  45. unsigned long get_board_ddr_clk(void)
  46. {
  47. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  48. switch ((ddrclk_conf & 0x30) >> 4) {
  49. case QIXIS_DDRCLK_100:
  50. return 100000000;
  51. case QIXIS_DDRCLK_125:
  52. return 125000000;
  53. case QIXIS_DDRCLK_133:
  54. return 133333333;
  55. }
  56. return 66666666;
  57. }
  58. void board_init_f(ulong bootflag)
  59. {
  60. u32 plat_ratio, sys_clk, ccb_clk;
  61. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  62. #if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
  63. /*
  64. * There is T1040 SoC issue where NOR, FPGA are inaccessible during
  65. * NAND boot because IFC signals > IFC_AD7 are not enabled.
  66. * This workaround changes RCW source to make all signals enabled.
  67. */
  68. u32 porsr1, pinctl;
  69. #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
  70. porsr1 = in_be32(&gur->porsr1);
  71. pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
  72. out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
  73. #endif
  74. /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  75. memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  76. /* Update GD pointer */
  77. gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  78. console_init_f();
  79. /* initialize selected port with appropriate baud rate */
  80. sys_clk = get_board_sys_clk();
  81. plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  82. ccb_clk = sys_clk * plat_ratio / 2;
  83. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  84. ccb_clk / 16 / CONFIG_BAUDRATE);
  85. #if defined(CONFIG_SPL_MMC_BOOT)
  86. puts("\nSD boot...\n");
  87. #elif defined(CONFIG_SPL_SPI_BOOT)
  88. puts("\nSPI boot...\n");
  89. #elif defined(CONFIG_SPL_NAND_BOOT)
  90. puts("\nNAND boot...\n");
  91. #endif
  92. relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  93. }
  94. void board_init_r(gd_t *gd, ulong dest_addr)
  95. {
  96. bd_t *bd;
  97. bd = (bd_t *)(gd + sizeof(gd_t));
  98. memset(bd, 0, sizeof(bd_t));
  99. gd->bd = bd;
  100. bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  101. bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  102. arch_cpu_init();
  103. get_clocks();
  104. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  105. CONFIG_SPL_RELOC_MALLOC_SIZE);
  106. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  107. #ifdef CONFIG_SPL_NAND_BOOT
  108. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  109. (uchar *)SPL_ENV_ADDR);
  110. #endif
  111. #ifdef CONFIG_SPL_MMC_BOOT
  112. mmc_initialize(bd);
  113. mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  114. (uchar *)SPL_ENV_ADDR);
  115. #endif
  116. #ifdef CONFIG_SPL_SPI_BOOT
  117. fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  118. (uchar *)SPL_ENV_ADDR);
  119. #endif
  120. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  121. gd->env_valid = ENV_VALID;
  122. i2c_init_all();
  123. dram_init();
  124. #ifdef CONFIG_SPL_MMC_BOOT
  125. mmc_boot();
  126. #elif defined(CONFIG_SPL_SPI_BOOT)
  127. fsl_spi_boot();
  128. #elif defined(CONFIG_SPL_NAND_BOOT)
  129. nand_boot();
  130. #endif
  131. }