spl.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <console.h>
  8. #include <env.h>
  9. #include <env_internal.h>
  10. #include <init.h>
  11. #include <ns16550.h>
  12. #include <malloc.h>
  13. #include <mmc.h>
  14. #include <nand.h>
  15. #include <i2c.h>
  16. #include "../common/ngpixis.h"
  17. #include <fsl_esdhc.h>
  18. #include <spi_flash.h>
  19. #include "../common/spl.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static const u32 sysclk_tbl[] = {
  22. 66666000, 7499900, 83332500, 8999900,
  23. 99999000, 11111000, 12499800, 13333200
  24. };
  25. phys_size_t get_effective_memsize(void)
  26. {
  27. return CONFIG_SYS_L2_SIZE;
  28. }
  29. void board_init_f(ulong bootflag)
  30. {
  31. int px_spd;
  32. u32 plat_ratio, sys_clk, bus_clk;
  33. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  34. console_init_f();
  35. /* Set pmuxcr to allow both i2c1 and i2c2 */
  36. setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
  37. setbits_be32(&gur->pmuxcr,
  38. in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  39. #ifdef CONFIG_SPL_SPI_BOOT
  40. /* Enable the SPI */
  41. clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
  42. #endif
  43. /* Read back the register to synchronize the write. */
  44. in_be32(&gur->pmuxcr);
  45. /* initialize selected port with appropriate baud rate */
  46. px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
  47. sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
  48. plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  49. bus_clk = sys_clk * plat_ratio / 2;
  50. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  51. bus_clk / 16 / CONFIG_BAUDRATE);
  52. #ifdef CONFIG_SPL_MMC_BOOT
  53. puts("\nSD boot...\n");
  54. #elif defined(CONFIG_SPL_SPI_BOOT)
  55. puts("\nSPI Flash boot...\n");
  56. #endif
  57. /* copy code to RAM and jump to it - this should not return */
  58. /* NOTE - code has to be copied out of NAND buffer before
  59. * other blocks can be read.
  60. */
  61. relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  62. }
  63. void board_init_r(gd_t *gd, ulong dest_addr)
  64. {
  65. /* Pointer is writable since we allocated a register for it */
  66. gd = (gd_t *)CONFIG_SPL_GD_ADDR;
  67. bd_t *bd;
  68. memset(gd, 0, sizeof(gd_t));
  69. bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
  70. memset(bd, 0, sizeof(bd_t));
  71. gd->bd = bd;
  72. bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
  73. bd->bi_memsize = CONFIG_SYS_L2_SIZE;
  74. arch_cpu_init();
  75. get_clocks();
  76. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  77. CONFIG_SPL_RELOC_MALLOC_SIZE);
  78. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  79. #ifndef CONFIG_SPL_NAND_BOOT
  80. env_init();
  81. #endif
  82. #ifdef CONFIG_SPL_MMC_BOOT
  83. mmc_initialize(bd);
  84. #endif
  85. /* relocate environment function pointers etc. */
  86. #ifdef CONFIG_SPL_NAND_BOOT
  87. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  88. (uchar *)SPL_ENV_ADDR);
  89. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  90. gd->env_valid = ENV_VALID;
  91. #else
  92. env_relocate();
  93. #endif
  94. #ifdef CONFIG_SYS_I2C
  95. i2c_init_all();
  96. #else
  97. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  98. #endif
  99. dram_init();
  100. #ifdef CONFIG_SPL_NAND_BOOT
  101. puts("Tertiary program loader running in sram...");
  102. #else
  103. puts("Second program loader running in sram...\n");
  104. #endif
  105. #ifdef CONFIG_SPL_MMC_BOOT
  106. mmc_boot();
  107. #elif defined(CONFIG_SPL_SPI_BOOT)
  108. fsl_spi_boot();
  109. #elif defined(CONFIG_SPL_NAND_BOOT)
  110. nand_boot();
  111. #endif
  112. }