mpc8313erdb.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <clock_legacy.h>
  9. #include <fdt_support.h>
  10. #include <init.h>
  11. #if defined(CONFIG_OF_LIBFDT)
  12. #include <linux/libfdt.h>
  13. #endif
  14. #include <pci.h>
  15. #include <mpc83xx.h>
  16. #include <vsc7385.h>
  17. #include <ns16550.h>
  18. #include <nand.h>
  19. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  20. #include <asm/gpio.h>
  21. #endif
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int board_early_init_f(void)
  24. {
  25. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  26. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  27. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  28. gd->flags |= GD_FLG_SILENT;
  29. #endif
  30. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  31. mpc83xx_gpio_init_f();
  32. #endif
  33. return 0;
  34. }
  35. int board_early_init_r(void)
  36. {
  37. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  38. mpc83xx_gpio_init_r();
  39. #endif
  40. return 0;
  41. }
  42. int checkboard(void)
  43. {
  44. puts("Board: Freescale MPC8313ERDB\n");
  45. return 0;
  46. }
  47. #ifndef CONFIG_SPL_BUILD
  48. static struct pci_region pci_regions[] = {
  49. {
  50. .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
  51. .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
  52. .size = CONFIG_SYS_PCI1_MEM_SIZE,
  53. .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
  54. },
  55. {
  56. .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
  57. .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
  58. .size = CONFIG_SYS_PCI1_MMIO_SIZE,
  59. .flags = PCI_REGION_MEM
  60. },
  61. {
  62. .bus_start = CONFIG_SYS_PCI1_IO_BASE,
  63. .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
  64. .size = CONFIG_SYS_PCI1_IO_SIZE,
  65. .flags = PCI_REGION_IO
  66. }
  67. };
  68. void pci_init_board(void)
  69. {
  70. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  71. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  72. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  73. struct pci_region *reg[] = { pci_regions };
  74. /* Enable all 3 PCI_CLK_OUTPUTs. */
  75. clk->occr |= 0xe0000000;
  76. /*
  77. * Configure PCI Local Access Windows
  78. */
  79. pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  80. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  81. pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  82. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  83. mpc83xx_pci_init(1, reg);
  84. }
  85. /*
  86. * Miscellaneous late-boot configurations
  87. *
  88. * If a VSC7385 microcode image is present, then upload it.
  89. */
  90. int misc_init_r(void)
  91. {
  92. int rc = 0;
  93. #ifdef CONFIG_VSC7385_IMAGE
  94. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  95. CONFIG_VSC7385_IMAGE_SIZE)) {
  96. puts("Failure uploading VSC7385 microcode.\n");
  97. rc = 1;
  98. }
  99. #endif
  100. return rc;
  101. }
  102. #if defined(CONFIG_OF_BOARD_SETUP)
  103. int ft_board_setup(void *blob, bd_t *bd)
  104. {
  105. ft_cpu_setup(blob, bd);
  106. #ifdef CONFIG_PCI
  107. ft_pci_setup(blob, bd);
  108. #endif
  109. return 0;
  110. }
  111. #endif
  112. #else /* CONFIG_SPL_BUILD */
  113. void board_init_f(ulong bootflag)
  114. {
  115. board_early_init_f();
  116. NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
  117. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  118. puts("NAND boot... ");
  119. timer_init();
  120. dram_init();
  121. relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
  122. CONFIG_SYS_NAND_U_BOOT_RELOC);
  123. }
  124. void board_init_r(gd_t *gd, ulong dest_addr)
  125. {
  126. nand_boot();
  127. }
  128. void putc(char c)
  129. {
  130. if (gd->flags & GD_FLG_SILENT)
  131. return;
  132. if (c == '\n')
  133. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
  134. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
  135. }
  136. #endif