lx2160a.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018-2019 NXP
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <dm.h>
  8. #include <dm/platform_data/serial_pl01x.h>
  9. #include <i2c.h>
  10. #include <malloc.h>
  11. #include <errno.h>
  12. #include <netdev.h>
  13. #include <fsl_ddr.h>
  14. #include <fsl_sec.h>
  15. #include <asm/io.h>
  16. #include <fdt_support.h>
  17. #include <linux/libfdt.h>
  18. #include <fsl-mc/fsl_mc.h>
  19. #include <env_internal.h>
  20. #include <efi_loader.h>
  21. #include <asm/arch/mmu.h>
  22. #include <hwconfig.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/config.h>
  25. #include <asm/arch/fsl_serdes.h>
  26. #include <asm/arch/soc.h>
  27. #include "../common/qixis.h"
  28. #include "../common/vid.h"
  29. #include <fsl_immap.h>
  30. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  31. #ifdef CONFIG_EMC2305
  32. #include "../common/emc2305.h"
  33. #endif
  34. #ifdef CONFIG_TARGET_LX2160AQDS
  35. #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
  36. #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
  37. #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
  38. #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
  39. #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
  40. #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
  41. #define SDHC1_BASE_PMUX_DSPI 2
  42. #define SDHC2_BASE_PMUX_DSPI 2
  43. #define IIC5_PMUX_SPI3 3
  44. #endif /* CONFIG_TARGET_LX2160AQDS */
  45. DECLARE_GLOBAL_DATA_PTR;
  46. static struct pl01x_serial_platdata serial0 = {
  47. #if CONFIG_CONS_INDEX == 0
  48. .base = CONFIG_SYS_SERIAL0,
  49. #elif CONFIG_CONS_INDEX == 1
  50. .base = CONFIG_SYS_SERIAL1,
  51. #else
  52. #error "Unsupported console index value."
  53. #endif
  54. .type = TYPE_PL011,
  55. };
  56. U_BOOT_DEVICE(nxp_serial0) = {
  57. .name = "serial_pl01x",
  58. .platdata = &serial0,
  59. };
  60. static struct pl01x_serial_platdata serial1 = {
  61. .base = CONFIG_SYS_SERIAL1,
  62. .type = TYPE_PL011,
  63. };
  64. U_BOOT_DEVICE(nxp_serial1) = {
  65. .name = "serial_pl01x",
  66. .platdata = &serial1,
  67. };
  68. int select_i2c_ch_pca9547(u8 ch)
  69. {
  70. int ret;
  71. #ifndef CONFIG_DM_I2C
  72. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  73. #else
  74. struct udevice *dev;
  75. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  76. if (!ret)
  77. ret = dm_i2c_write(dev, 0, &ch, 1);
  78. #endif
  79. if (ret) {
  80. puts("PCA: failed to select proper channel\n");
  81. return ret;
  82. }
  83. return 0;
  84. }
  85. static void uart_get_clock(void)
  86. {
  87. serial0.clock = get_serial_clock();
  88. serial1.clock = get_serial_clock();
  89. }
  90. int board_early_init_f(void)
  91. {
  92. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  93. i2c_early_init_f();
  94. #endif
  95. /* get required clock for UART IP */
  96. uart_get_clock();
  97. #ifdef CONFIG_EMC2305
  98. select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
  99. emc2305_init();
  100. set_fan_speed(I2C_EMC2305_PWM);
  101. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  102. #endif
  103. fsl_lsch3_early_init_f();
  104. return 0;
  105. }
  106. #ifdef CONFIG_OF_BOARD_FIXUP
  107. int board_fix_fdt(void *fdt)
  108. {
  109. char *reg_names, *reg_name;
  110. int names_len, old_name_len, new_name_len, remaining_names_len;
  111. struct str_map {
  112. char *old_str;
  113. char *new_str;
  114. } reg_names_map[] = {
  115. { "ccsr", "dbi" },
  116. { "pf_ctrl", "ctrl" }
  117. };
  118. int off = -1, i;
  119. if (IS_SVR_REV(get_svr(), 1, 0))
  120. return 0;
  121. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
  122. while (off != -FDT_ERR_NOTFOUND) {
  123. fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
  124. strlen("fsl,ls-pcie") + 1);
  125. reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
  126. &names_len);
  127. if (!reg_names)
  128. continue;
  129. reg_name = reg_names;
  130. remaining_names_len = names_len - (reg_name - reg_names);
  131. for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
  132. old_name_len = strlen(reg_names_map[i].old_str);
  133. new_name_len = strlen(reg_names_map[i].new_str);
  134. if (memcmp(reg_name, reg_names_map[i].old_str,
  135. old_name_len) == 0) {
  136. /* first only leave required bytes for new_str
  137. * and copy rest of the string after it
  138. */
  139. memcpy(reg_name + new_name_len,
  140. reg_name + old_name_len,
  141. remaining_names_len - old_name_len);
  142. /* Now copy new_str */
  143. memcpy(reg_name, reg_names_map[i].new_str,
  144. new_name_len);
  145. names_len -= old_name_len;
  146. names_len += new_name_len;
  147. }
  148. reg_name = memchr(reg_name, '\0', remaining_names_len);
  149. if (!reg_name)
  150. break;
  151. reg_name += 1;
  152. remaining_names_len = names_len -
  153. (reg_name - reg_names);
  154. }
  155. fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
  156. off = fdt_node_offset_by_compatible(fdt, off,
  157. "fsl,lx2160a-pcie");
  158. }
  159. return 0;
  160. }
  161. #endif
  162. #if defined(CONFIG_TARGET_LX2160AQDS)
  163. void esdhc_dspi_status_fixup(void *blob)
  164. {
  165. const char esdhc0_path[] = "/soc/esdhc@2140000";
  166. const char esdhc1_path[] = "/soc/esdhc@2150000";
  167. const char dspi0_path[] = "/soc/dspi@2100000";
  168. const char dspi1_path[] = "/soc/dspi@2110000";
  169. const char dspi2_path[] = "/soc/dspi@2120000";
  170. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  171. u32 sdhc1_base_pmux;
  172. u32 sdhc2_base_pmux;
  173. u32 iic5_pmux;
  174. /* Check RCW field sdhc1_base_pmux to enable/disable
  175. * esdhc0/dspi0 DT node
  176. */
  177. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  178. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  179. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  180. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  181. do_fixup_by_path(blob, dspi0_path, "status", "okay",
  182. sizeof("okay"), 1);
  183. do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
  184. sizeof("disabled"), 1);
  185. } else {
  186. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  187. sizeof("okay"), 1);
  188. do_fixup_by_path(blob, dspi0_path, "status", "disabled",
  189. sizeof("disabled"), 1);
  190. }
  191. /* Check RCW field sdhc2_base_pmux to enable/disable
  192. * esdhc1/dspi1 DT node
  193. */
  194. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  195. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  196. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  197. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  198. do_fixup_by_path(blob, dspi1_path, "status", "okay",
  199. sizeof("okay"), 1);
  200. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  201. sizeof("disabled"), 1);
  202. } else {
  203. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  204. sizeof("okay"), 1);
  205. do_fixup_by_path(blob, dspi1_path, "status", "disabled",
  206. sizeof("disabled"), 1);
  207. }
  208. /* Check RCW field IIC5 to enable dspi2 DT node */
  209. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  210. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  211. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  212. if (iic5_pmux == IIC5_PMUX_SPI3) {
  213. do_fixup_by_path(blob, dspi2_path, "status", "okay",
  214. sizeof("okay"), 1);
  215. }
  216. }
  217. #endif
  218. int esdhc_status_fixup(void *blob, const char *compat)
  219. {
  220. #if defined(CONFIG_TARGET_LX2160AQDS)
  221. /* Enable esdhc and dspi DT nodes based on RCW fields */
  222. esdhc_dspi_status_fixup(blob);
  223. #else
  224. /* Enable both esdhc DT nodes for LX2160ARDB */
  225. do_fixup_by_compat(blob, compat, "status", "okay",
  226. sizeof("okay"), 1);
  227. #endif
  228. return 0;
  229. }
  230. #if defined(CONFIG_VID)
  231. int i2c_multiplexer_select_vid_channel(u8 channel)
  232. {
  233. return select_i2c_ch_pca9547(channel);
  234. }
  235. int init_func_vid(void)
  236. {
  237. if (adjust_vdd(0) < 0)
  238. printf("core voltage not adjusted\n");
  239. return 0;
  240. }
  241. #endif
  242. int checkboard(void)
  243. {
  244. enum boot_src src = get_boot_src();
  245. char buf[64];
  246. u8 sw;
  247. #ifdef CONFIG_TARGET_LX2160AQDS
  248. int clock;
  249. static const char *const freq[] = {"100", "125", "156.25",
  250. "161.13", "322.26", "", "", "",
  251. "", "", "", "", "", "", "",
  252. "100 separate SSCG"};
  253. #endif
  254. cpu_name(buf);
  255. #ifdef CONFIG_TARGET_LX2160AQDS
  256. printf("Board: %s-QDS, ", buf);
  257. #else
  258. printf("Board: %s-RDB, ", buf);
  259. #endif
  260. sw = QIXIS_READ(arch);
  261. printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
  262. if (src == BOOT_SOURCE_SD_MMC) {
  263. puts("SD\n");
  264. } else {
  265. sw = QIXIS_READ(brdcfg[0]);
  266. sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
  267. switch (sw) {
  268. case 0:
  269. case 4:
  270. puts("FlexSPI DEV#0\n");
  271. break;
  272. case 1:
  273. puts("FlexSPI DEV#1\n");
  274. break;
  275. case 2:
  276. case 3:
  277. puts("FlexSPI EMU\n");
  278. break;
  279. default:
  280. printf("invalid setting, xmap: %d\n", sw);
  281. break;
  282. }
  283. }
  284. #ifdef CONFIG_TARGET_LX2160AQDS
  285. printf("FPGA: v%d (%s), build %d",
  286. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  287. (int)qixis_read_minor());
  288. /* the timestamp string contains "\n" at the end */
  289. printf(" on %s", qixis_read_time(buf));
  290. puts("SERDES1 Reference : ");
  291. sw = QIXIS_READ(brdcfg[2]);
  292. clock = sw >> 4;
  293. printf("Clock1 = %sMHz ", freq[clock]);
  294. clock = sw & 0x0f;
  295. printf("Clock2 = %sMHz", freq[clock]);
  296. sw = QIXIS_READ(brdcfg[3]);
  297. puts("\nSERDES2 Reference : ");
  298. clock = sw >> 4;
  299. printf("Clock1 = %sMHz ", freq[clock]);
  300. clock = sw & 0x0f;
  301. printf("Clock2 = %sMHz", freq[clock]);
  302. sw = QIXIS_READ(brdcfg[12]);
  303. puts("\nSERDES3 Reference : ");
  304. clock = sw >> 4;
  305. printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
  306. #else
  307. printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
  308. puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
  309. puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  310. puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
  311. #endif
  312. return 0;
  313. }
  314. #ifdef CONFIG_TARGET_LX2160AQDS
  315. /*
  316. * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
  317. */
  318. u8 qixis_esdhc_detect_quirk(void)
  319. {
  320. /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
  321. * SDHC1 Card ID:
  322. * Specifies the type of card installed in the SDHC1 adapter slot.
  323. * 000= (reserved)
  324. * 001= eMMC V4.5 adapter is installed.
  325. * 010= SD/MMC 3.3V adapter is installed.
  326. * 011= eMMC V4.4 adapter is installed.
  327. * 100= eMMC V5.0 adapter is installed.
  328. * 101= MMC card/Legacy (3.3V) adapter is installed.
  329. * 110= SDCard V2/V3 adapter installed.
  330. * 111= no adapter is installed.
  331. */
  332. return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
  333. QIXIS_ESDHC_NO_ADAPTER);
  334. }
  335. int config_board_mux(void)
  336. {
  337. u8 reg11, reg5, reg13;
  338. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  339. u32 sdhc1_base_pmux;
  340. u32 sdhc2_base_pmux;
  341. u32 iic5_pmux;
  342. /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
  343. * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
  344. * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
  345. * Qixis and remote systems are isolated from the I2C1 bus.
  346. * Processor connections are still available.
  347. * SPI2 CS2_B controls EN25S64 SPI memory device.
  348. * SPI3 CS2_B controls EN25S64 SPI memory device.
  349. * EC2 connects to PHY #2 using RGMII protocol.
  350. * CLK_OUT connects to FPGA for clock measurement.
  351. */
  352. reg5 = QIXIS_READ(brdcfg[5]);
  353. reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
  354. QIXIS_WRITE(brdcfg[5], reg5);
  355. /* Check RCW field sdhc1_base_pmux
  356. * esdhc0 : sdhc1_base_pmux = 0
  357. * dspi0 : sdhc1_base_pmux = 2
  358. */
  359. sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  360. & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
  361. sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
  362. if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
  363. reg11 = QIXIS_READ(brdcfg[11]);
  364. reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
  365. QIXIS_WRITE(brdcfg[11], reg11);
  366. } else {
  367. /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
  368. * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
  369. * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
  370. */
  371. reg11 = QIXIS_READ(brdcfg[11]);
  372. reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
  373. QIXIS_WRITE(brdcfg[11], reg11);
  374. }
  375. /* Check RCW field sdhc2_base_pmux
  376. * esdhc1 : sdhc2_base_pmux = 0 (default)
  377. * dspi1 : sdhc2_base_pmux = 2
  378. */
  379. sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
  380. & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
  381. sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
  382. if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
  383. reg13 = QIXIS_READ(brdcfg[13]);
  384. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
  385. QIXIS_WRITE(brdcfg[13], reg13);
  386. } else {
  387. reg13 = QIXIS_READ(brdcfg[13]);
  388. reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
  389. QIXIS_WRITE(brdcfg[13], reg13);
  390. }
  391. /* Check RCW field IIC5 to enable dspi2 DT nodei
  392. * dspi2: IIC5 = 3
  393. */
  394. iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
  395. & FSL_CHASSIS3_IIC5_PMUX_MASK;
  396. iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
  397. if (iic5_pmux == IIC5_PMUX_SPI3) {
  398. /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
  399. reg11 = QIXIS_READ(brdcfg[11]);
  400. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
  401. QIXIS_WRITE(brdcfg[11], reg11);
  402. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
  403. * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
  404. * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
  405. */
  406. reg11 = QIXIS_READ(brdcfg[11]);
  407. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
  408. QIXIS_WRITE(brdcfg[11], reg11);
  409. } else {
  410. /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
  411. reg11 = QIXIS_READ(brdcfg[11]);
  412. reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
  413. QIXIS_WRITE(brdcfg[11], reg11);
  414. /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
  415. * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
  416. * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
  417. */
  418. reg11 = QIXIS_READ(brdcfg[11]);
  419. reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
  420. QIXIS_WRITE(brdcfg[11], reg11);
  421. }
  422. return 0;
  423. }
  424. #elif defined(CONFIG_TARGET_LX2160ARDB)
  425. int config_board_mux(void)
  426. {
  427. u8 brdcfg;
  428. brdcfg = QIXIS_READ(brdcfg[4]);
  429. /* The BRDCFG4 register controls general board configuration.
  430. *|-------------------------------------------|
  431. *|Field | Function |
  432. *|-------------------------------------------|
  433. *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
  434. *|CAN_EN | 0= CAN transceivers are disabled. |
  435. *| | 1= CAN transceivers are enabled. |
  436. *|-------------------------------------------|
  437. */
  438. brdcfg |= BIT_MASK(5);
  439. QIXIS_WRITE(brdcfg[4], brdcfg);
  440. return 0;
  441. }
  442. #else
  443. int config_board_mux(void)
  444. {
  445. return 0;
  446. }
  447. #endif
  448. unsigned long get_board_sys_clk(void)
  449. {
  450. #ifdef CONFIG_TARGET_LX2160AQDS
  451. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  452. switch (sysclk_conf & 0x03) {
  453. case QIXIS_SYSCLK_100:
  454. return 100000000;
  455. case QIXIS_SYSCLK_125:
  456. return 125000000;
  457. case QIXIS_SYSCLK_133:
  458. return 133333333;
  459. }
  460. return 100000000;
  461. #else
  462. return 100000000;
  463. #endif
  464. }
  465. unsigned long get_board_ddr_clk(void)
  466. {
  467. #ifdef CONFIG_TARGET_LX2160AQDS
  468. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  469. switch ((ddrclk_conf & 0x30) >> 4) {
  470. case QIXIS_DDRCLK_100:
  471. return 100000000;
  472. case QIXIS_DDRCLK_125:
  473. return 125000000;
  474. case QIXIS_DDRCLK_133:
  475. return 133333333;
  476. }
  477. return 100000000;
  478. #else
  479. return 100000000;
  480. #endif
  481. }
  482. int board_init(void)
  483. {
  484. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  485. u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
  486. #endif
  487. #ifdef CONFIG_ENV_IS_NOWHERE
  488. gd->env_addr = (ulong)&default_environment[0];
  489. #endif
  490. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  491. #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
  492. /* invert AQR107 IRQ pins polarity */
  493. out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
  494. #endif
  495. #ifdef CONFIG_FSL_CAAM
  496. sec_init();
  497. #endif
  498. return 0;
  499. }
  500. void detail_board_ddr_info(void)
  501. {
  502. int i;
  503. u64 ddr_size = 0;
  504. puts("\nDDR ");
  505. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  506. ddr_size += gd->bd->bi_dram[i].size;
  507. print_size(ddr_size, "");
  508. print_ddr_info(0);
  509. }
  510. #if defined(CONFIG_ARCH_MISC_INIT)
  511. int arch_misc_init(void)
  512. {
  513. config_board_mux();
  514. return 0;
  515. }
  516. #endif
  517. #ifdef CONFIG_FSL_MC_ENET
  518. extern int fdt_fixup_board_phy(void *fdt);
  519. void fdt_fixup_board_enet(void *fdt)
  520. {
  521. int offset;
  522. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  523. if (offset < 0)
  524. offset = fdt_path_offset(fdt, "/fsl-mc");
  525. if (offset < 0) {
  526. printf("%s: fsl-mc node not found in device tree (error %d)\n",
  527. __func__, offset);
  528. return;
  529. }
  530. if (get_mc_boot_status() == 0 &&
  531. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
  532. fdt_status_okay(fdt, offset);
  533. fdt_fixup_board_phy(fdt);
  534. } else {
  535. fdt_status_fail(fdt, offset);
  536. }
  537. }
  538. void board_quiesce_devices(void)
  539. {
  540. fsl_mc_ldpaa_exit(gd->bd);
  541. }
  542. #endif
  543. #ifdef CONFIG_OF_BOARD_SETUP
  544. int ft_board_setup(void *blob, bd_t *bd)
  545. {
  546. int i;
  547. u16 mc_memory_bank = 0;
  548. u64 *base;
  549. u64 *size;
  550. u64 mc_memory_base = 0;
  551. u64 mc_memory_size = 0;
  552. u16 total_memory_banks;
  553. ft_cpu_setup(blob, bd);
  554. fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
  555. if (mc_memory_base != 0)
  556. mc_memory_bank++;
  557. total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
  558. base = calloc(total_memory_banks, sizeof(u64));
  559. size = calloc(total_memory_banks, sizeof(u64));
  560. /* fixup DT for the three GPP DDR banks */
  561. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  562. base[i] = gd->bd->bi_dram[i].start;
  563. size[i] = gd->bd->bi_dram[i].size;
  564. }
  565. #ifdef CONFIG_RESV_RAM
  566. /* reduce size if reserved memory is within this bank */
  567. if (gd->arch.resv_ram >= base[0] &&
  568. gd->arch.resv_ram < base[0] + size[0])
  569. size[0] = gd->arch.resv_ram - base[0];
  570. else if (gd->arch.resv_ram >= base[1] &&
  571. gd->arch.resv_ram < base[1] + size[1])
  572. size[1] = gd->arch.resv_ram - base[1];
  573. else if (gd->arch.resv_ram >= base[2] &&
  574. gd->arch.resv_ram < base[2] + size[2])
  575. size[2] = gd->arch.resv_ram - base[2];
  576. #endif
  577. if (mc_memory_base != 0) {
  578. for (i = 0; i <= total_memory_banks; i++) {
  579. if (base[i] == 0 && size[i] == 0) {
  580. base[i] = mc_memory_base;
  581. size[i] = mc_memory_size;
  582. break;
  583. }
  584. }
  585. }
  586. fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
  587. #ifdef CONFIG_USB
  588. fsl_fdt_fixup_dr_usb(blob, bd);
  589. #endif
  590. #ifdef CONFIG_FSL_MC_ENET
  591. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  592. fdt_fixup_board_enet(blob);
  593. #endif
  594. fdt_fixup_icid(blob);
  595. return 0;
  596. }
  597. #endif
  598. void qixis_dump_switch(void)
  599. {
  600. int i, nr_of_cfgsw;
  601. QIXIS_WRITE(cms[0], 0x00);
  602. nr_of_cfgsw = QIXIS_READ(cms[1]);
  603. puts("DIP switch settings dump:\n");
  604. for (i = 1; i <= nr_of_cfgsw; i++) {
  605. QIXIS_WRITE(cms[0], i);
  606. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  607. }
  608. }