ls1021atsn.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright 2016-2019 NXP Semiconductors
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <fdt_support.h>
  7. #include <init.h>
  8. #include <asm/arch-ls102xa/ls102xa_soc.h>
  9. #include <asm/arch/ls102xa_devdis.h>
  10. #include <asm/arch/immap_ls102xa.h>
  11. #include <asm/arch/ls102xa_soc.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include "../common/sleep.h"
  14. #include <fsl_validate.h>
  15. #include <fsl_immap.h>
  16. #include <fsl_csu.h>
  17. #include <netdev.h>
  18. #include <spl.h>
  19. #ifdef CONFIG_U_QE
  20. #include <fsl_qe.h>
  21. #endif
  22. DECLARE_GLOBAL_DATA_PTR;
  23. static void ddrmc_init(void)
  24. {
  25. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  26. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  27. u32 temp_sdram_cfg, tmp;
  28. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  29. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  30. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  31. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  32. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  33. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  34. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  35. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  36. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  37. #ifdef CONFIG_DEEP_SLEEP
  38. if (is_warm_boot()) {
  39. out_be32(&ddr->sdram_cfg_2,
  40. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  41. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  42. out_be32(&ddr->init_ext_addr, (1 << 31));
  43. /* DRAM VRef will not be trained */
  44. out_be32(&ddr->ddr_cdr2,
  45. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  46. } else
  47. #endif
  48. {
  49. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  50. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  51. }
  52. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  53. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  54. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  55. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  56. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  57. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  58. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  59. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  60. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  61. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  62. /* DDR erratum A-009942 */
  63. tmp = in_be32(&ddr->debug[28]);
  64. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  65. udelay(1);
  66. #ifdef CONFIG_DEEP_SLEEP
  67. if (is_warm_boot()) {
  68. /* enter self-refresh */
  69. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  70. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  71. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  72. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  73. } else
  74. #endif
  75. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  76. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  77. #ifdef CONFIG_DEEP_SLEEP
  78. if (is_warm_boot()) {
  79. /* exit self-refresh */
  80. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  81. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  82. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  83. }
  84. #endif
  85. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  86. }
  87. int dram_init(void)
  88. {
  89. ddrmc_init();
  90. erratum_a008850_post();
  91. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  92. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  93. fsl_dp_resume();
  94. #endif
  95. return 0;
  96. }
  97. int board_eth_init(bd_t *bis)
  98. {
  99. return pci_eth_init(bis);
  100. }
  101. int board_early_init_f(void)
  102. {
  103. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  104. #ifdef CONFIG_TSEC_ENET
  105. /*
  106. * Clear BD & FR bits for big endian BD's and frame data (aka set
  107. * correct eTSEC endianness). This is crucial in ensuring that it does
  108. * not report Data Parity Errors in its RX/TX FIFOs when attempting to
  109. * send traffic.
  110. */
  111. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  112. /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
  113. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  114. #endif
  115. arch_soc_init();
  116. #if defined(CONFIG_DEEP_SLEEP)
  117. if (is_warm_boot()) {
  118. timer_init();
  119. dram_init();
  120. }
  121. #endif
  122. return 0;
  123. }
  124. #ifdef CONFIG_SPL_BUILD
  125. void board_init_f(ulong dummy)
  126. {
  127. void (*second_uboot)(void);
  128. /* Clear the BSS */
  129. memset(__bss_start, 0, __bss_end - __bss_start);
  130. get_clocks();
  131. #if defined(CONFIG_DEEP_SLEEP)
  132. if (is_warm_boot())
  133. fsl_dp_disable_console();
  134. #endif
  135. preloader_console_init();
  136. dram_init();
  137. /* Allow OCRAM access permission as R/W */
  138. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  139. enable_layerscape_ns_access();
  140. enable_layerscape_ns_access();
  141. #endif
  142. /*
  143. * if it is woken up from deep sleep, then jump to second
  144. * stage U-Boot and continue executing without recopying
  145. * it from SD since it has already been reserved in memory
  146. * in last boot.
  147. */
  148. if (is_warm_boot()) {
  149. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  150. second_uboot();
  151. }
  152. board_init_r(NULL, 0);
  153. }
  154. #endif
  155. int board_init(void)
  156. {
  157. #ifndef CONFIG_SYS_FSL_NO_SERDES
  158. fsl_serdes_init();
  159. #endif
  160. ls102xa_smmu_stream_id_init();
  161. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  162. enable_layerscape_ns_access();
  163. #endif
  164. #ifdef CONFIG_U_QE
  165. u_qe_init();
  166. #endif
  167. return 0;
  168. }
  169. #if defined(CONFIG_SPL_BUILD)
  170. void spl_board_init(void)
  171. {
  172. ls102xa_smmu_stream_id_init();
  173. }
  174. #endif
  175. #ifdef CONFIG_BOARD_LATE_INIT
  176. int board_late_init(void)
  177. {
  178. #ifdef CONFIG_CHAIN_OF_TRUST
  179. fsl_setenv_chain_of_trust();
  180. #endif
  181. return 0;
  182. }
  183. #endif
  184. #if defined(CONFIG_MISC_INIT_R)
  185. int misc_init_r(void)
  186. {
  187. #ifdef CONFIG_FSL_DEVICE_DISABLE
  188. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  189. #endif
  190. #ifdef CONFIG_FSL_CAAM
  191. return sec_init();
  192. #endif
  193. }
  194. #endif
  195. #if defined(CONFIG_DEEP_SLEEP)
  196. void board_sleep_prepare(void)
  197. {
  198. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  199. enable_layerscape_ns_access();
  200. #endif
  201. }
  202. #endif
  203. int ft_board_setup(void *blob, bd_t *bd)
  204. {
  205. ft_cpu_setup(blob, bd);
  206. #ifdef CONFIG_PCI
  207. ft_pci_setup(blob, bd);
  208. #endif
  209. return 0;
  210. }