ls1021aqds.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <fdt_support.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/immap_ls102xa.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include <asm/arch/ls102xa_soc.h>
  15. #include <asm/arch/ls102xa_devdis.h>
  16. #include <hwconfig.h>
  17. #include <mmc.h>
  18. #include <fsl_csu.h>
  19. #include <fsl_ifc.h>
  20. #include <fsl_sec.h>
  21. #include <spl.h>
  22. #include <fsl_devdis.h>
  23. #include <fsl_validate.h>
  24. #include <fsl_ddr.h>
  25. #include "../common/sleep.h"
  26. #include "../common/qixis.h"
  27. #include "ls1021aqds_qixis.h"
  28. #ifdef CONFIG_U_QE
  29. #include <fsl_qe.h>
  30. #endif
  31. #define PIN_MUX_SEL_CAN 0x03
  32. #define PIN_MUX_SEL_IIC2 0xa0
  33. #define PIN_MUX_SEL_RGMII 0x00
  34. #define PIN_MUX_SEL_SAI 0x0c
  35. #define PIN_MUX_SEL_SDHC 0x00
  36. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
  37. #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  38. enum {
  39. MUX_TYPE_CAN,
  40. MUX_TYPE_IIC2,
  41. MUX_TYPE_RGMII,
  42. MUX_TYPE_SAI,
  43. MUX_TYPE_SDHC,
  44. MUX_TYPE_SD_PCI4,
  45. MUX_TYPE_SD_PC_SA_SG_SG,
  46. MUX_TYPE_SD_PC_SA_PC_SG,
  47. MUX_TYPE_SD_PC_SG_SG,
  48. };
  49. enum {
  50. GE0_CLK125,
  51. GE2_CLK125,
  52. GE1_CLK125,
  53. };
  54. int checkboard(void)
  55. {
  56. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  57. char buf[64];
  58. #endif
  59. #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  60. u8 sw;
  61. #endif
  62. puts("Board: LS1021AQDS\n");
  63. #ifdef CONFIG_SD_BOOT
  64. puts("SD\n");
  65. #elif CONFIG_QSPI_BOOT
  66. puts("QSPI\n");
  67. #else
  68. sw = QIXIS_READ(brdcfg[0]);
  69. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  70. if (sw < 0x8)
  71. printf("vBank: %d\n", sw);
  72. else if (sw == 0x8)
  73. puts("PromJet\n");
  74. else if (sw == 0x9)
  75. puts("NAND\n");
  76. else if (sw == 0x15)
  77. printf("IFCCard\n");
  78. else
  79. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  80. #endif
  81. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  82. printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  83. QIXIS_READ(id), QIXIS_READ(arch));
  84. printf("FPGA: v%d (%s), build %d\n",
  85. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  86. (int)qixis_read_minor());
  87. #endif
  88. return 0;
  89. }
  90. unsigned long get_board_sys_clk(void)
  91. {
  92. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  93. switch (sysclk_conf & 0x0f) {
  94. case QIXIS_SYSCLK_64:
  95. return 64000000;
  96. case QIXIS_SYSCLK_83:
  97. return 83333333;
  98. case QIXIS_SYSCLK_100:
  99. return 100000000;
  100. case QIXIS_SYSCLK_125:
  101. return 125000000;
  102. case QIXIS_SYSCLK_133:
  103. return 133333333;
  104. case QIXIS_SYSCLK_150:
  105. return 150000000;
  106. case QIXIS_SYSCLK_160:
  107. return 160000000;
  108. case QIXIS_SYSCLK_166:
  109. return 166666666;
  110. }
  111. return 66666666;
  112. }
  113. unsigned long get_board_ddr_clk(void)
  114. {
  115. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  116. switch ((ddrclk_conf & 0x30) >> 4) {
  117. case QIXIS_DDRCLK_100:
  118. return 100000000;
  119. case QIXIS_DDRCLK_125:
  120. return 125000000;
  121. case QIXIS_DDRCLK_133:
  122. return 133333333;
  123. }
  124. return 66666666;
  125. }
  126. int select_i2c_ch_pca9547(u8 ch)
  127. {
  128. int ret;
  129. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  130. if (ret) {
  131. puts("PCA: failed to select proper channel\n");
  132. return ret;
  133. }
  134. return 0;
  135. }
  136. int dram_init(void)
  137. {
  138. /*
  139. * When resuming from deep sleep, the I2C channel may not be
  140. * in the default channel. So, switch to the default channel
  141. * before accessing DDR SPD.
  142. */
  143. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  144. return fsl_initdram();
  145. }
  146. int board_early_init_f(void)
  147. {
  148. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  149. #ifdef CONFIG_TSEC_ENET
  150. /* clear BD & FR bits for BE BD's and frame data */
  151. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  152. #endif
  153. #ifdef CONFIG_FSL_IFC
  154. init_early_memctl_regs();
  155. #endif
  156. arch_soc_init();
  157. #if defined(CONFIG_DEEP_SLEEP)
  158. if (is_warm_boot())
  159. fsl_dp_disable_console();
  160. #endif
  161. return 0;
  162. }
  163. #ifdef CONFIG_SPL_BUILD
  164. void board_init_f(ulong dummy)
  165. {
  166. #ifdef CONFIG_NAND_BOOT
  167. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  168. u32 porsr1, pinctl;
  169. /*
  170. * There is LS1 SoC issue where NOR, FPGA are inaccessible during
  171. * NAND boot because IFC signals > IFC_AD7 are not enabled.
  172. * This workaround changes RCW source to make all signals enabled.
  173. */
  174. porsr1 = in_be32(&gur->porsr1);
  175. pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
  176. DCFG_CCSR_PORSR1_RCW_SRC_I2C);
  177. out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  178. pinctl);
  179. #endif
  180. /* Clear the BSS */
  181. memset(__bss_start, 0, __bss_end - __bss_start);
  182. #ifdef CONFIG_FSL_IFC
  183. init_early_memctl_regs();
  184. #endif
  185. get_clocks();
  186. #if defined(CONFIG_DEEP_SLEEP)
  187. if (is_warm_boot())
  188. fsl_dp_disable_console();
  189. #endif
  190. preloader_console_init();
  191. #ifdef CONFIG_SPL_I2C_SUPPORT
  192. i2c_init_all();
  193. #endif
  194. timer_init();
  195. dram_init();
  196. /* Allow OCRAM access permission as R/W */
  197. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  198. enable_layerscape_ns_access();
  199. #endif
  200. board_init_r(NULL, 0);
  201. }
  202. #endif
  203. void config_etseccm_source(int etsec_gtx_125_mux)
  204. {
  205. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  206. switch (etsec_gtx_125_mux) {
  207. case GE0_CLK125:
  208. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
  209. debug("etseccm set to GE0_CLK125\n");
  210. break;
  211. case GE2_CLK125:
  212. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  213. debug("etseccm set to GE2_CLK125\n");
  214. break;
  215. case GE1_CLK125:
  216. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
  217. debug("etseccm set to GE1_CLK125\n");
  218. break;
  219. default:
  220. printf("Error! trying to set etseccm to invalid value\n");
  221. break;
  222. }
  223. }
  224. int config_board_mux(int ctrl_type)
  225. {
  226. u8 reg12, reg14;
  227. reg12 = QIXIS_READ(brdcfg[12]);
  228. reg14 = QIXIS_READ(brdcfg[14]);
  229. switch (ctrl_type) {
  230. case MUX_TYPE_CAN:
  231. config_etseccm_source(GE2_CLK125);
  232. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
  233. break;
  234. case MUX_TYPE_IIC2:
  235. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
  236. break;
  237. case MUX_TYPE_RGMII:
  238. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
  239. break;
  240. case MUX_TYPE_SAI:
  241. config_etseccm_source(GE2_CLK125);
  242. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
  243. break;
  244. case MUX_TYPE_SDHC:
  245. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
  246. break;
  247. case MUX_TYPE_SD_PCI4:
  248. reg12 = 0x38;
  249. break;
  250. case MUX_TYPE_SD_PC_SA_SG_SG:
  251. reg12 = 0x01;
  252. break;
  253. case MUX_TYPE_SD_PC_SA_PC_SG:
  254. reg12 = 0x01;
  255. break;
  256. case MUX_TYPE_SD_PC_SG_SG:
  257. reg12 = 0x21;
  258. break;
  259. default:
  260. printf("Wrong mux interface type\n");
  261. return -1;
  262. }
  263. QIXIS_WRITE(brdcfg[12], reg12);
  264. QIXIS_WRITE(brdcfg[14], reg14);
  265. return 0;
  266. }
  267. int config_serdes_mux(void)
  268. {
  269. struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
  270. u32 cfg;
  271. cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  272. cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  273. switch (cfg) {
  274. case 0x0:
  275. config_board_mux(MUX_TYPE_SD_PCI4);
  276. break;
  277. case 0x30:
  278. config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
  279. break;
  280. case 0x60:
  281. config_board_mux(MUX_TYPE_SD_PC_SG_SG);
  282. break;
  283. case 0x70:
  284. config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
  285. break;
  286. default:
  287. printf("SRDS1 prtcl:0x%x\n", cfg);
  288. break;
  289. }
  290. return 0;
  291. }
  292. #ifdef CONFIG_BOARD_LATE_INIT
  293. int board_late_init(void)
  294. {
  295. #ifdef CONFIG_CHAIN_OF_TRUST
  296. fsl_setenv_chain_of_trust();
  297. #endif
  298. return 0;
  299. }
  300. #endif
  301. int misc_init_r(void)
  302. {
  303. int conflict_flag;
  304. /* some signals can not enable simultaneous*/
  305. conflict_flag = 0;
  306. if (hwconfig("sdhc"))
  307. conflict_flag++;
  308. if (hwconfig("iic2"))
  309. conflict_flag++;
  310. if (conflict_flag > 1) {
  311. printf("WARNING: pin conflict !\n");
  312. return 0;
  313. }
  314. conflict_flag = 0;
  315. if (hwconfig("rgmii"))
  316. conflict_flag++;
  317. if (hwconfig("can"))
  318. conflict_flag++;
  319. if (hwconfig("sai"))
  320. conflict_flag++;
  321. if (conflict_flag > 1) {
  322. printf("WARNING: pin conflict !\n");
  323. return 0;
  324. }
  325. if (hwconfig("can"))
  326. config_board_mux(MUX_TYPE_CAN);
  327. else if (hwconfig("rgmii"))
  328. config_board_mux(MUX_TYPE_RGMII);
  329. else if (hwconfig("sai"))
  330. config_board_mux(MUX_TYPE_SAI);
  331. if (hwconfig("iic2"))
  332. config_board_mux(MUX_TYPE_IIC2);
  333. else if (hwconfig("sdhc"))
  334. config_board_mux(MUX_TYPE_SDHC);
  335. #ifdef CONFIG_FSL_DEVICE_DISABLE
  336. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  337. #endif
  338. #ifdef CONFIG_FSL_CAAM
  339. return sec_init();
  340. #endif
  341. return 0;
  342. }
  343. int board_init(void)
  344. {
  345. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  346. erratum_a010315();
  347. #endif
  348. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  349. erratum_a009942_check_cpo();
  350. #endif
  351. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  352. #ifndef CONFIG_SYS_FSL_NO_SERDES
  353. fsl_serdes_init();
  354. config_serdes_mux();
  355. #endif
  356. ls102xa_smmu_stream_id_init();
  357. #ifdef CONFIG_U_QE
  358. u_qe_init();
  359. #endif
  360. return 0;
  361. }
  362. #if defined(CONFIG_DEEP_SLEEP)
  363. void board_sleep_prepare(void)
  364. {
  365. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  366. enable_layerscape_ns_access();
  367. #endif
  368. }
  369. #endif
  370. int ft_board_setup(void *blob, bd_t *bd)
  371. {
  372. ft_cpu_setup(blob, bd);
  373. #ifdef CONFIG_PCI
  374. ft_pci_setup(blob, bd);
  375. #endif
  376. return 0;
  377. }
  378. u8 flash_read8(void *addr)
  379. {
  380. return __raw_readb(addr + 1);
  381. }
  382. void flash_write16(u16 val, void *addr)
  383. {
  384. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  385. __raw_writew(shftval, addr);
  386. }
  387. u16 flash_read16(void *addr)
  388. {
  389. u16 val = __raw_readw(addr);
  390. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  391. }